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An eight-bit prefetch circuit for high-bandwidth DRAM's.
Toshio Sunaga
Koji Hosokawa
Yutaka Nakamura
Manabu Ichinose
Yasuyuki Igarashi
Published in:
IEEE J. Solid State Circuits (1997)
Keyphrases
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high bandwidth
high density
low voltage
random access memory
end to end
low latency
high speed
data center
application specific
cmos technology
main memory
supply chain
parallel processing