Hisatada Miyatake

Publication Activity (10 Years)

Years Active: 1996-2001
Publications (10 Years): 0

Publications

Hisatada Miyatake, Masahiro Tanaka, Yotaro Mori
A design for high-speed low-power CMOS fully parallel content-addressable memory macros. IEEE J. Solid State Circuits 36 (6) (2001)
Toshio Sunaga, Hisatada Miyatake, Koji Kitamura, Peter M. Kogge, Eric Retter
A parallel processing chip with embedded DRAM macros. IEEE J. Solid State Circuits 31 (10) (1996)