A design for high-speed low-power CMOS fully parallel content-addressable memory macros.
Hisatada MiyatakeMasahiro TanakaYotaro MoriPublished in: IEEE J. Solid State Circuits (2001)
Keyphrases
- low power
- high speed
- single chip
- power consumption
- low power consumption
- vlsi architecture
- logic circuits
- cmos technology
- low cost
- content addressable memory
- mixed signal
- digital signal processing
- ultra low power
- nm technology
- power dissipation
- gate array
- vlsi circuits
- delay insensitive
- power reduction
- real time
- circuit design
- computer architecture
- parallel processing
- cmos image sensor
- rate distortion
- analog to digital converter
- general purpose