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A parallel processing chip with embedded DRAM macros.
Toshio Sunaga
Hisatada Miyatake
Koji Kitamura
Peter M. Kogge
Eric Retter
Published in:
IEEE J. Solid State Circuits (1996)
Keyphrases
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parallel processing
embedded dram
cmos technology
random access memory
computational power
dynamic random access memory
low voltage
distributed processing
parallel computation
memory subsystem
real time
low power
cmos image sensor
metal oxide semiconductor
design considerations