Theo J. Powell

Publication Activity (10 Years)

Years Active: 1982-2006
Publications (10 Years): 0

Publications

Aman Kokrady, Theo J. Powell, S. Ramakrishnan
Reducing Design Verification Cycle Time through Testbench Redundancy. VLSI Design (2006)
Theo J. Powell, Amrendra Kumar, Joseph Rayhawk, Nilanjan Mukherjee
Chasing subtle embedded RAM defects for nanometer technologies. ITC (2005)
Theo J. Powell, Wu-Tung Cheng, Joseph Rayhawk, Omer Samman, Paul Policke, Sherry Lai
BIST for Deep Submicron ASIC Memories with High Performance Application. ITC (2003)
Theo J. Powell, James R. Pair, Melissa St. John, Doug Counce
Delta Iddq for Testing Reliability. VTS (2000)
Theo J. Powell, Dan Cline, Francis Hii
A 256Meg SDRAM BIST for Disturb Test Application. ITC (1997)
Theo J. Powell
Consistently dominant fault model for tristate buffer nets. VTS (1996)
Theo J. Powell, James R. Pair, Bernard G. Carbajal III
Tests. ITC (1996)
Graham Hetherington, Greg Sutton, Kenneth M. Butler, Theo J. Powell
Test Generation and Design for Test for a Large Multiprocessing DSP. ITC (1995)
Theo J. Powell, Kenneth M. Butler, Mike Ales, Roy Haley, Mark Perry
Correlating defect level to final test fault coverage for modular structured designs [microcontroller family]. VTS (1994)
Theo J. Powell, Fred Hwang, Bill Johnson
Testability Features in the TMS370 Family of Microcomputers. ITC (1988)
Thirumalai Sridhar, D. S. Ho, Theo J. Powell, Satish M. Thatte
Analysis and Simulation of Parallel Signature Analyzers. ITC (1982)
Satish M. Thatte, D. S. Ho, H.-T. Yuan, Thirumalai Sridhar, Theo J. Powell
An Architecture for Testable VLSI Processors. ITC (1982)