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Takeshi Tokuda
Publication Activity (10 Years)
Years Active: 1983-1993
Publications (10 Years): 0
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Publications
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Eiichi Teraoka
,
Toru Kengaku
,
Ikuo Yasui
,
Kazuyuki Ishikawa
,
Takahiro Matsuo
,
Hideyuki Wakada
,
Narumi Sakashita
,
Yukihiko Shimazu
,
Takeshi Tokuda
A Built-in Self- Test for ADC and DAC in a Single-Chip Speech CODEC.
ITC
(1993)
Kazuo Nakamura
,
Narumi Sakashita
,
Yasuhiko Nitta
,
Ken'ichi Shimomura
,
Takeshi Tokuda
Fuzzy inference and fuzzy inference processor.
IEEE Micro
13 (5) (1993)
Toshiyuki Tamura
,
Shinji Komori
,
Fumiyasu Asai
,
Hirono Tsubota
,
Hisakazu Sato
,
Hidehiro Takata
,
Yoshihiro Seguchi
,
Takeshi Tokuda
,
Hiroaki Terada
A Data-Driven Architecture for Distributed Parallel Processing.
ICCD
(1991)
Narumi Sakashita
,
Hisako Sawai
,
Eiichi Teraoka
,
Toshiki Fugiyama
,
Toru Kengaku
,
Yukihiko Shimazu
,
Takeshi Tokuda
Built-in self-test in a 24 bit floating point digital signal processor.
ITC
(1990)
Takeshi Tokuda
,
Jiro Korematsu
,
Yukihiko Shimazu
,
Narumi Sakashita
,
Tohru Kengaku
,
Toshiki Fugiyama
,
Takio Ohno
,
Osamu Tomisawa
A macrocell approach for VLSI processor design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
7 (12) (1988)
Takeshi Tokuda
,
Jiro Korematsu
,
Osamu Tomisawa
,
Sotoju Asai
,
Isao Ohkura
,
Tatsuya Enomoto
A Hierarchical Standard Cell Approach for Custom VLSI Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
3 (3) (1984)
Takeshi Tokuda
,
Kaoru Okazaki
,
Kazuhiro Sakashita
,
Isao Ohkura
,
Tatsuya Enomoto
Delay-Time Modeling for ED MOS Logic LSI.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
2 (3) (1983)