Kaoru Okazaki

Publication Activity (10 Years)

Years Active: 1981-1998
Publications (10 Years): 0

Publications

Hiroshi Shirota, Toshiyuki Sadakane, Masayuki Terai, Kaoru Okazaki
A new router for reducing "antenna effect" in ASIC design. CICC (1998)
Satoshi Shibatani, Toshiyuki Sadakane, Hiroomi Nakao, Masayuki Terai, Kaoru Okazaki
A CMOS cell generation system for two-dimensional transistor placement. CICC (1998)
Takeshi Tokuda, Kaoru Okazaki, Kazuhiro Sakashita, Isao Ohkura, Tatsuya Enomoto
Delay-Time Modeling for ED MOS Logic LSI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2 (3) (1983)
Kaoru Okazaki, Tomoko Moriya, Toshihiko Yahara
A multiple media delay simulator for MOS LSI circuits. DAC (1983)
Chiyoji Tanaka, Shinichi Murai, Hiroo Tsuji, Toshihiko Yahara, Kaoru Okazaki, Masayuki Terai, Reiji Katoh, Mikio Tachibana
An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3. DAC (1981)
Kaoru Okazaki, Toshihiko Yahara
Efficient Logic Verification and Test Validation for MOS LSI Circuits. ITC (1981)