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A CMOS cell generation system for two-dimensional transistor placement.
Satoshi Shibatani
Toshiyuki Sadakane
Hiroomi Nakao
Masayuki Terai
Kaoru Okazaki
Published in:
CICC (1998)
Keyphrases
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image processing
high speed
low power
low cost
power consumption
three dimensional
integrated circuit
circuit design
power dissipation
multi dimensional
generation process
generation method
power supply
delay insensitive
information systems