Takahiro Nagano

Publication Activity (10 Years)

Years Active: 1995-1996
Publications (10 Years): 0

Publications

Hiroyuki Mizuno, Takahiro Nagano
Driving source-line cell architecture for sub-1-V high-speed low-power applications. IEEE J. Solid State Circuits 31 (4) (1996)
Koichiro Ishibashi, Kunihiro Komiyaji, Hiroshi Toyoshima, Masataka Minami, Nagatoshi Ohki, Hiroshi Ishida, Toshiaki Yamanaka, Takahiro Nagano, Takashi Nishida
A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL. IEEE J. Solid State Circuits 30 (11) (1995)
Koichiro Ishibashi, Koichi Takasugi, Kunihiro Komiyaji, Hiroshi Toyoshima, Toshiaki Yamanaka, Akira Fukami, Naotaka Hashimoto, Nagatoshi Ohki, Akihiro Shimizu, Takashi Hashimoto, Takahiro Nagano, Takashi Nishida
A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers. IEEE J. Solid State Circuits 30 (4) (1995)