Driving source-line cell architecture for sub-1-V high-speed low-power applications.
Hiroyuki MizunoTakahiro NaganoPublished in: IEEE J. Solid State Circuits (1996)
Keyphrases
- low power
- high speed
- vlsi architecture
- power consumption
- low cost
- cmos technology
- single chip
- mixed signal
- real time
- nm technology
- wireless transmission
- high power
- gate array
- signal processor
- vlsi circuits
- logic circuits
- frame rate
- low power consumption
- digital signal processing
- image sensor
- power reduction
- delay insensitive
- associative memory