A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL.
Koichiro IshibashiKunihiro KomiyajiHiroshi ToyoshimaMasataka MinamiNagatoshi OhkiHiroshi IshidaToshiaki YamanakaTakahiro NaganoTakashi NishidaPublished in: IEEE J. Solid State Circuits (1995)
Keyphrases
- cmos technology
- power consumption
- nm technology
- low power
- high speed
- random access memory
- low voltage
- level set
- times faster
- clock frequency
- low cost
- power dissipation
- piecewise constant
- processing pipeline
- pipeline architecture
- image sensor
- level set method
- parallel processing
- framework for image segmentation
- single chip
- inter frame
- power reduction
- design considerations
- power management
- real time
- data transmission
- vlsi circuits
- cmos image sensor