A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers.
Koichiro IshibashiKoichi TakasugiKunihiro KomiyajiHiroshi ToyoshimaToshiaki YamanakaAkira FukamiNaotaka HashimotoNagatoshi OhkiAkihiro ShimizuTakashi HashimotoTakahiro NaganoTakashi NishidaPublished in: IEEE J. Solid State Circuits (1995)