Suresh Purini

Publication Activity (10 Years)

Years Active: 2007-2024
Publications (10 Years): 27

Top Topics

Programming Assignments

Image Processing

Interval Analysis

Coalition Formation

Top Venues

Publications

Shashwat Khandelwal, Ziaul Choudhury, Shashwat Shrivastava, Suresh Purini
Accelerating local laplacian filters on FPGAs. CoRR (2024)
Ziaul Choudhury, Anish Gulati, Suresh Purini
FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler. ACM Trans. Archit. Code Optim. 20 (4) (2023)
Shaarada D. Yamini, Mirishkar Sai Ganesh, Anil Kumar Vuppala, Suresh Purini
Hardware Accelerator for Transformer based End-to-End Automatic Speech Recognition System. IPDPS Workshops (2023)
Kunal Jain, Kishan Sairam Adapa, Kunwar Grover, Ravi Kiran Sarvadevabhatla, Suresh Purini
A Cloud-Fog Architecture for Video Analytics on Large Scale Camera Networks Using Semantic Scene Analysis. CCGrid (2023)
Vaibhav Kashera, Siddhant Jain, Abhishek Banerjee, Suresh Purini
Building Low-Latency Order Books with Hybrid Binary-Linear Search Data Structures on FPGAs. FPL (2023)
Prithvi Velicheti, Sivani Pentapati, Suresh Purini
Systolic Array based FPGA accelerator for Yolov3-tiny. HPEC (2022)
Ziaul Choudhury, Shashwat Shrivastava, Lavanya Ramapantulu, Suresh Purini
An FPGA Overlay for CNN Inference with Fine-grained Flexible Parallelism. ACM Trans. Archit. Code Optim. 19 (3) (2022)
Shivani Maurya, Ziaul Choudhury, Suresh Purini
Accuracy Configurable FPGA Implementation of Harris Corner Detection. ISVLSI (2022)
Yash Khandelwal, Arushi Dogra, Karthik Ganti, Suresh Purini, Puduru V. Reddy
Pricing strategies of an oligopolist in federated cloud markets. J. Cloud Comput. 10 (1) (2021)
Surya Teja Palavalasa, Yuvraj Singh, Adhish Singla, Suresh Purini, Venkatesh Choppella
Model Checking as a Service using Dynamic Resource Scaling. HiPC (2020)
Shashwat Khandelwal, Ziaul Choudhury, Shashwat Shrivastava, Suresh Purini
Accelerating Local Laplacian Filters on FPGAs. FPL (2020)
Suresh Purini, Vinamra Benara, Ziaul Choudhury, Uday Bondhugula
Bitwidth customization in image processing pipelines using interval analysis and SMT solvers. CC (2020)
Shashwat Shrivastava, Ziaul Choudhury, Shashwat Khandelwal, Suresh Purini
FPGA Accelerator for Stereo Vision using Semi-Global Matching through Dependency Relaxation. FPL (2020)
Shrenik Jain, Suresh Purini, Puduru V. Reddy
A Multi-Cloud Marketplace Model with Multiple Brokers for IaaS Layer and Generalized Stable Matching. UCC (2018)
Vinamra Benara, Sahithi Rampalli, Ziaul Choudhury, Suresh Purini, Uday Bondhugula
Synthesizing Power and Area Efficient Image Processing Pipelines on FPGAs using Customized Bit-widths. CoRR (2018)
Deepak Awasthi, Syed Azeemuddin, Suresh Purini, Annesha Mazumder
Flow Sensor IoT Node for Wi-Fi Equipped Apartments and Gated Communities. IEEE SENSORS (2018)
Yash Khandelwal, Karthik Ganti, Suresh Purini, Puduru V. Reddy
Cloud Federation Formation in Oligopolistic Markets. Euro-Par (2018)
Shaleen Garg, Kishore Kothapalli, Suresh Purini
Share-a-GPU: Providing Simple and Effective Time-Sharing on GPUs. HiPC (2018)
Jitendra Yasaswi, Sri Kailash, Anil Chilupuri, Suresh Purini, C. V. Jawahar
Unsupervised Learning Based Approach for Plagiarism Detection in Programming Assignments. ISEC (2017)
Jitendra Yasaswi, Suresh Purini, C. V. Jawahar
Plagiarism Detection in Programming Assignments Using Deep Features. ACPR (2017)
Adhish Singla, Krishnaji Desai, Suresh Purini, Venkatesh Choppella
Distributed Safety Verification Using Vertex Centric Programming Model. ISPDC (2016)
Nehal J. Wani, Sharada Prasanna Mohanty, Suresh Purini, Dipti Misra Sharma
Anuvaad Pranaali: A RESTful API for Machine Translation. ICSOC Workshops (2016)
Ronak Kogta, Suresh Purini, Ajit Mathew
Re-targeting Optimization Sequences from Scalar Processors to FPGAs in HLS compilers (Abstract Only). FPGA (2016)
Ziaul Choudhury, Suresh Purini, Shiva Rama Krishna
A Hybrid CPU+GPU Working-Set Dictionary. ISPDC (2016)
Yash Khandelwal, Suresh Purini, Puduru V. Reddy
Fast algorithms for optimal coalition formation in federated clouds. UCC (2016)
Vinamra Benara, Suresh Purini
Accurus: A Fast Convergence Technique for Accuracy Configurable Approximate Adder Circuits. ISVLSI (2016)
Nitin Chugh, Vinay Vasista, Suresh Purini, Uday Bondhugula
A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs. PACT (2016)
Kapil Kumar, Nehal J. Wani, Suresh Purini
Dynamic Memory and Core Scaling in Virtual Machines. CLOUD (2015)
Sanidhya Kashyap, Jaspal Singh Dhillon, Suresh Purini
RLC - A Reliable Approach to Fast and Efficient Live Migration of Virtual Machines in the Clouds. IEEE CLOUD (2014)
Suresh Purini, Lakshya Jain
Finding good optimization sequences covering program space. ACM Trans. Archit. Code Optim. 9 (4) (2013)
Jaspal Singh Dhillon, Suresh Purini, Sanidhya Kashyap
Virtual Machine Coscheduling: A Game Theoretic Approach. UCC (2013)
Bharghava Rajaram, Abinesh Ramachandran, Suresh Purini, R. Govindatajulu
Design of Low Power Systems Using Inexact Logic Circuits. J. Low Power Electron. 6 (3) (2010)
Bharghava Rajaram, Abinesh Ramachandran, Suresh Purini, Govindarajulu Regeti
Inexact Decision Circuits: An Application to Hamming Weight Threshold Voting. VLSI Design (2010)
Abinesh Ramachandran, Bharghava Rajaram, Suresh Purini, Govindarajulu Regeti
Transition Inversion Based Low Power Data Coding Scheme for Buffered Data Transfer. VLSI Design (2010)
Richard Chang, Suresh Purini
Amplifying ZPP^SAT[1] and the Two Queries Problem. Computational Complexity Conference (2008)
Richard Chang, Suresh Purini
Bounded Queries and the NP Machine Hypothesis. Computational Complexity Conference (2007)