Systolic Array based FPGA accelerator for Yolov3-tiny.

Prithvi Velicheti Sivani Pentapati Suresh Purini

Published in: HPEC (2022)

Keyphrases

systolic array
reconfigurable architecture
parallel architecture
data flow
parallel implementation
field programmable gate array
hardware implementation
compute intensive
lower bound
database systems
parallel processing
distributed memory