Uday Bondhugula

Publication Activity (10 Years)

Years Active: 2005-2023
Publications (10 Years): 28

Top Topics

Intermediate Representation

Image Processing

Top Venues

ACM Trans. Program. Lang. Syst.

Publications

Kingshuk Majumder, Uday Bondhugula
Automatic multi-dimensional pipelining for high-level synthesis of dataflow accelerators. CoRR (2023)
Kingshuk Majumder, Uday Bondhugula
HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description. ASPLOS (4) (2023)
Navdeep Katel, Vivek Khandelwal, Uday Bondhugula
MLIR-based code generation for GPU tensor cores. CC (2022)
Ashwin Prasad, Sampath Rajendra, Kaushik Rajan, R. Govindarajan, Uday Bondhugula
Treebeard: An Optimizing Compiler for Decision Tree Based ML Inference. MICRO (2022)
Kumudha Narasimhan, Aravind Acharya, Abhinav Baid, Uday Bondhugula
A practical tile size selection model for affine loop nests. ICS (2021)
Navdeep Katel, Vivek Khandelwal, Uday Bondhugula
High Performance GPU Code Generation for Matrix-Matrix Multiplication using MLIR: Some Early Results. CoRR (2021)
Chris Lattner, Mehdi Amini, Uday Bondhugula, Albert Cohen, Andy Davis, Jacques A. Pienaar, River Riddle, Tatiana Shpeisman, Nicolas Vasilache, Oleksandr Zinenko
MLIR: Scaling Compiler Infrastructure for Domain Specific Computation. CGO (2021)
Kingshuk Majumder, Uday Bondhugula
HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description. CoRR (2021)
Aravind Acharya, Uday Bondhugula, Albert Cohen
Effective Loop Fusion in Polyhedral Compilation Using Fusion Conflict Graphs. ACM Trans. Archit. Code Optim. 17 (4) (2020)
Suresh Purini, Vinamra Benara, Ziaul Choudhury, Uday Bondhugula
Bitwidth customization in image processing pipelines using interval analysis and SMT solvers. CC (2020)
Karan Aggarwal, Uday Bondhugula
Optimizing the Linear Fascicle Evaluation Algorithm for Multi-core and Many-core Systems. ACM Trans. Parallel Comput. 7 (4) (2020)
Abhinav Jangda, Uday Bondhugula
An Effective Fusion and Tile Size Model for PolyMage. ACM Trans. Program. Lang. Syst. 42 (3) (2020)
Uday Bondhugula
High Performance Code Generation in MLIR: An Early Case Study with GEMM. CoRR (2020)
Chris Lattner, Jacques A. Pienaar, Mehdi Amini, Uday Bondhugula, River Riddle, Albert Cohen, Tatiana Shpeisman, Andy Davis, Nicolas Vasilache, Oleksandr Zinenko
MLIR: A Compiler Infrastructure for the End of Moore's Law. CoRR (2020)
Kingshuk Majumder, Uday Bondhugula
A flexible FPGA accelerator for convolutional neural networks. CoRR (2019)
Karan Aggarwal, Uday Bondhugula
Optimizing the linear fascicle evaluation algorithm for many-core systems. ICS (2019)
Karan Aggarwal, Uday Bondhugula, Varsha Sreenivasan, Devarajan Sridharan
Optimizing the Linear Fascicle Evaluation Algorithm for Multi-Core and Many-Core Systems. CoRR (2019)
Abhinav Jangda, Uday Bondhugula
An effective fusion and tile size model for optimizing image processing pipelines. PPOPP (2018)
Vinamra Benara, Sahithi Rampalli, Ziaul Choudhury, Suresh Purini, Uday Bondhugula
Synthesizing Power and Area Efficient Image Processing Pipelines on FPGAs using Customized Bit-widths. CoRR (2018)
Aravind Acharya, Uday Bondhugula, Albert Cohen
Polyhedral auto-transformation with no integer linear programming. PLDI (2018)
Aravind Acharya, Uday Bondhugula, Albert Cohen
An Approach for Finding Permutations Quickly: Fusion and Dimension matching. CoRR (2018)
Uday Bondhugula, Vinayaka Bandishti, Irshad Pananilath
Diamond Tiling: Tiling Techniques to Maximize Parallelism for Stencil Computations. IEEE Trans. Parallel Distributed Syst. 28 (5) (2017)
Vinay Vasista, Kumudha Narasimhan, Siddharth Bhat, Uday Bondhugula
Optimizing geometric multigrid method computation using a DSL approach. SC (2017)
Somashekaracharya G. Bhaskaracharya, Uday Bondhugula, Albert Cohen
SMO: an integrated approach to intra-array and inter-array storage optimization. POPL (2016)
Roshan Dathathri, Ravi Teja Mullapudi, Uday Bondhugula
Compiling Affine Loop Nests for a Dynamic Scheduling Runtime on Shared and Distributed Memory. ACM Trans. Parallel Comput. 3 (2) (2016)
Uday Bondhugula, Aravind Acharya, Albert Cohen
The Pluto+ Algorithm: A Practical Approach for Parallelization and Locality Optimization of Affine Loop Nests. ACM Trans. Program. Lang. Syst. 38 (3) (2016)
Nitin Chugh, Vinay Vasista, Suresh Purini, Uday Bondhugula
A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs. PACT (2016)
Somashekaracharya G. Bhaskaracharya, Uday Bondhugula, Albert Cohen
Automatic Storage Optimization for Arrays. ACM Trans. Program. Lang. Syst. 38 (3) (2016)
Irshad Pananilath, Aravind Acharya, Vinay Vasista, Uday Bondhugula
An Optimizing Code Generator for a Class of Lattice-Boltzmann Computations. ACM Trans. Archit. Code Optim. 12 (2) (2015)
Ravi Teja Mullapudi, Vinay Vasista, Uday Bondhugula
PolyMage: Automatic Optimization for Image Processing Pipelines. ASPLOS (2015)
Aravind Acharya, Uday Bondhugula
PLUTO+: near-complete modeling of affine transformations for parallelism and locality. PPOPP (2015)
Chandan Reddy, Uday Bondhugula
Effective automatic computation placement and dataallocation for parallelization of regular programs. ICS (2014)
Uday Bondhugula, Vinayaka Bandishti, Albert Cohen, Guillain Potron, Nicolas Vasilache
Tiling and optimizing time-iterated computations on periodic domains. PACT (2014)
Uday Bondhugula
Compiling affine loop nests for distributed-memory parallel architectures. SC (2013)
Thejas Ramashekar, Uday Bondhugula
Automatic data allocation and buffer management for multi-GPU machines. ACM Trans. Archit. Code Optim. 10 (4) (2013)
Roshan Dathathri, Chandan Reddy, Thejas Ramashekar, Uday Bondhugula
Generating efficient data movement code for heterogeneous architectures with distributed-memory. PACT (2013)
Somashekaracharya G. Bhaskaracharya, Uday Bondhugula
PolyGLoT: A Polyhedral Loop Transformation Framework for a Graphical Dataflow Language. CC (2013)
Vinayaka Bandishti, Irshad Pananilath, Uday Bondhugula
Tiling stencil computations to maximize parallelism. SC (2012)
Louis-Noël Pouchet, Uday Bondhugula, Cédric Bastoul, Albert Cohen, J. Ramanujam, P. Sadayappan, Nicolas Vasilache
Loop transformations: convexity, pruning and optimization. POPL (2011)
Uday Bondhugula, Oktay Günlük, Sanjeeb Dash, Lakshminarayanan Renganarayanan
A model for fusion and code motion in an automatic parallelizing compiler. PACT (2010)
Rajesh Bordawekar, Uday Bondhugula, Ravi Rao
Believe it or not!: mult-core CPUs can match GPU performance for a FLOP-intensive application! PACT (2010)
Louis-Noël Pouchet, Uday Bondhugula, Cédric Bastoul, Albert Cohen, J. Ramanujam, P. Sadayappan
Combined Iterative and Model-driven Optimization in an Automatic Parallelization Framework. SC (2010)
Lakshminarayanan Renganarayanan, Uday Bondhugula, Salem Derisavi, Alexandre E. Eichenberger, Kevin O'Brien
Compact multi-dimensional kernel extraction for register tiling. SC (2009)
Muthu Manikandan Baskaran, Nagavijayalakshmi Vydyanathan, Uday Bondhugula, J. Ramanujam, Atanas Rountev, P. Sadayappan
Compiler-assisted dynamic scheduling for effective parallelization of loop nests on multicore processors. PPOPP (2009)
Qingda Lu, Christophe Alias, Uday Bondhugula, Thomas Henretty, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan, Yongjian Chen, Haibo Lin, Tin-fook Ngai
Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors. PACT (2009)
Muthu Manikandan Baskaran, Uday Bondhugula, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan
Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories. PPOPP (2008)
Uday Bondhugula, Albert Hartono, J. Ramanujam, P. Sadayappan
A practical automatic polyhedral parallelizer and locality optimizer. PLDI (2008)
Uday Bondhugula, Muthu Manikandan Baskaran, Albert Hartono, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan
Towards effective automatic parallelization for multicore systems. IPDPS (2008)
Muthu Manikandan Baskaran, Uday Bondhugula, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan
A compiler framework for optimization of affine loop nests for gpgpus. ICS (2008)
Uday Bondhugula, Muthu Manikandan Baskaran, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan
Automatic Transformations for Communication-Minimized Parallelization and Locality Optimization in the Polyhedral Model. CC (2008)
Sriram Krishnamoorthy, Muthu Manikandan Baskaran, Uday Bondhugula, J. Ramanujam, Atanas Rountev, P. Sadayappan
Effective automatic parallelization of stencil computations. PLDI (2007)
Uday Bondhugula, J. Ramanujam, P. Sadayappan
Automatic mapping of nested loops to FPGAS. PPOPP (2007)
Uday Bondhugula, Ananth Devulapalli, Joseph Fernando, Pete Wyckoff, P. Sadayappan
Parallel FPGA-based all-pairs shortest-paths in a directed graph. IPDPS (2006)
Uday Bondhugula, Ananth Devulapalli, James Dinan, Joseph Fernando, Pete Wyckoff, Eric Stahlberg, P. Sadayappan
Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths. FCCM (2006)
Sayantan Sur, Uday Bondhugula, Amith R. Mamidala, Hyun-Wook Jin, Dhabaleswar K. Panda
High Performance RDMA Based All-to-All Broadcast for InfiniBand Clusters. HiPC (2005)