Simon M. Tam

Publication Activity (10 Years)

Years Active: 1992-2018
Publications (10 Years): 1

Top Topics

Enterprise Architecture

Parallel Processing

Functional Verification

Competitive Advantage

Top Venues

IEEE J. Solid State Circuits

Publications

Simon M. Tam, Harry Muljono, Min Huang, Sitaraman Iyer, Kalapi Royneogi, Nagmohan Satti, Rizwan Qureshi, Wei Chen, Tom Wang, Hubert Hsieh, Sujal Vora, Eddie Wang
SkyLake-SP: A 14nm 28-Core xeon® processor. ISSCC (2018)
Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang
A 22 nm 15-Core Enterprise Xeon® Processor Family. IEEE J. Solid State Circuits 50 (1) (2015)
Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang
5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family. ISSCC (2014)
Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora
A 45 nm 8-Core Enterprise Xeon¯ Processor. IEEE J. Solid State Circuits 45 (1) (2010)
Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora
Power reduction techniques for an 8-core xeon® processor. ESSCIRC (2009)
Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli
A 45nm 8-core enterprise Xeon® processor. ISSCC (2009)
Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang, Brian S. Cherkauer, Jason Stinson, John Benoit, Raj Varada, Justin Leung, Rahul Dilip Limaye, Sujal Vora
A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache. IEEE J. Solid State Circuits 42 (1) (2007)
Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang
A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache. ISSCC (2006)
Utpal Desai, Simon M. Tam, Robert Kim, Ji Zhang, Stefan Rusu
Itanium processor clock design. ISPD (2000)
Jeff Brauch, Simon M. Tam, Mark A. Holler, Arthur L. Shmurun
Analog VLSI neural networks for impact signal processing. IEEE Micro 12 (6) (1992)