Sitaraman Iyer

Publication Activity (10 Years)

Years Active: 2010-2020
Publications (10 Years): 3

Top Topics

Power Management

Parallel Processing

Top Venues

Publications

Mike Bichan, Clifford Ting, Bahram Zand, Jing Wang, Ruslana Shulyzki, James Guthrie, Katya Tyshchenko, Junhong Zhao, Alireza Parsafar, Eric Liu, Aynaz Vatankhahghadim, Shaham Sharifian, Aleksey Tyshchenko, Michael De Vita, Syed Rubab, Sitaraman Iyer, Fulvio Spagna, Noam Dolev
A 32Gb/s NRZ 37dB SerDes in 10nm CMOS to Support PCI Express Gen 5 Protocol. CICC (2020)
Shenggao Li, Fulvio Spagna, Ji Chen, Xiaoqing Wang, Luke Tong, Sujatha Gowder, Wenyan Jia, Roan Nicholson, Sitaraman Iyer, Rui Song, Lily Li, Meng-hung Chen, Amanda Tran, Michael De Vita, Deepar Govindrajan, Marcus Pasquarella, Dave Bradley, Frank Verdico, Matt Duwe, Eric Lee, Michelle Wigton
A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS. A-SSCC (2018)
Simon M. Tam, Harry Muljono, Min Huang, Sitaraman Iyer, Kalapi Royneogi, Nagmohan Satti, Rizwan Qureshi, Wei Chen, Tom Wang, Hubert Hsieh, Sujal Vora, Eddie Wang
SkyLake-SP: A 14nm 28-Core xeon® processor. ISSCC (2018)
Fulvio Spagna, Lidong Chen, Mamatha Deshpande, Yongping Fan, Doug Gambetta, Sujatha Gowder, Sitaraman Iyer, Rohit Kumar, Peter Kwok, Renuka Krishnamurthy, Chien-chun Lin, Ravindran Mohanavelu, Roan Nicholson, Jeff Ou, Marcus Pasquarella, Kavitha Prasad, Hendra Rustam, Luke Tong, Amanda Tran, John Wu, Xuguang Zhang
A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS. ISSCC (2010)