Shunichi Toida

Publication Activity (10 Years)

Years Active: 1973-2006
Publications (10 Years): 0

Publications

Chutima Boonthum, Shunichi Toida, Irwin B. Levinstein
Preposition Senses: Generalized Disambiguation Model. CICLing (2006)
Nageswara S. V. Rao, Shunichi Toida
On Polynomial-Time Testable Combinational Circuits. IEEE Trans. Computers 43 (11) (1994)
Shunichi Toida
Revisiting shift register realization for ease of test generation and testing. VTS (1993)
Shunichi Toida, Nageswara S. V. Rao
On test generation for combinational circuits consisting of AND and EXOR gates. VTS (1992)
Nageswara S. V. Rao, Shunichi Toida
Computational Complexity of Test-Point Insertions and Decompositions. VLSI Design (1992)
Nageswara S. V. Rao, Shunichi Toida
On polynomial-time testable classes of combinational circuits. VTS (1991)
Hideo Fujiwara, Shunichi Toida
The Complexity of Fault Detection Problems for Combinational Logic Circuits. IEEE Trans. Computers 31 (6) (1982)
Toshihide Ibaraki, Tsunehiko Kameda, Shunichi Toida
On Minimal Test Sets for Locating Single Link Failures in Networks. IEEE Trans. Computers 30 (3) (1981)
Shunichi Toida
A note on Ádám's conjecture. J. Comb. Theory, Ser. B 23 (2-3) (1977)
Shunichi Toida
System Diagnosis and Redundant Tests. IEEE Trans. Computers 25 (11) (1976)
Tiko Kameda, Shunichi Toida, F. J. Allan
A Diagnosing Algorithm for Networks Inf. Control. 29 (2) (1975)
F. J. Allan, Tiko Kameda, Shunichi Toida
An Approach to the Diagnosability Analysis of a System. IEEE Trans. Computers 24 (10) (1975)
Tiko Kameda, Shunichi Toida
Efficient Algorithms for Determining an Extremal Tree of a Graph (Extended Abstract) SWAT (1973)
Shunichi Toida
Generation of all Cutsets of a Bipath Network. IEEE Trans. Commun. 21 (12) (1973)