Shingo Yoshizawa

Publication Activity (10 Years)

Years Active: 2004-2023
Publications (10 Years): 14

Top Topics

Vlsi Implementation

Underwater Acoustic

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Yuki Yamada, Shingo Yoshizawa, Takashi Saito, Hideki Sugimoto
Iterative Variable Threshold Method Resistant to Acoustic Reflections for Underwater Acoustic Positioning Systems. ISCIT (2023)
Shingo Yoshizawa, Hiroshi Tsutsui
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106 (3) (2023)
Etou Hiromu, Shingo Yoshizawa
Automatic Discrimination of Sound Propagation Path Using CNN for Underwater Acoustic Communication. ISCIT (2021)
Takahiro Ishikawa, Shingo Yoshizawa
RAKE Reception of OFDM Signals in Non-Line-of-Sight Underwater Acoustic Communication. ISPACS (2021)
Atsushi Wada, Shingo Yoshizawa, Satoshi Yuasa, Hideki Sugimoto
Simultaneous Multi-points Measurement in Underwater Acoustic Localization. ISPACS (2021)
Shingo Yoshizawa, Takashi Saito, Yusaku Mabuchi, Tomoya Tsukui, Shin-ichi Sawada
Parallel Resampling of OFDM Signals for Fluctuating Doppler Shifts in Underwater Acoustic Communication. J. Electr. Comput. Eng. 2018 (2018)
Shingo Yoshizawa, Hiroshi Tanimoto, Takashi Saito
Data Selective Rake Reception for Underwater Acoustic Communication in Strong Multipath Interference. J. Electr. Comput. Eng. 2017 (2017)
Tatsuya Abe, Hiroshi Tanimoto, Shingo Yoshizawa
A simple current reference with low sensitivity to supply voltage and temperature. MIXDES (2017)
Tran Thi Thao Nguyen, Leonardo Lanante, Yuhei Nagao, Masayuki Kurosaki, Shingo Yoshizawa, Hiroshi Ochi
Interleaved Domain Interference Canceller for Low Latency IDMA System and Its VLSI Implementation. VTC Spring (2017)
Tran Thi Thao Nguyen, Leonardo Lanante, Shingo Yoshizawa, Hiroshi Ochi
Low Latency IDMA With Interleaved Domain Architecture for 5G Communications. IEEE J. Emerg. Sel. Topics Circuits Syst. 7 (4) (2017)
Tran Thi Thao Nguyen, Leonardo Lanante, Yuhei Nagao, Masayuki Kurosaki, Shingo Yoshizawa, Hiroshi Ochi
Low latency Interleave Division Multiple Access System. ICOIN (2017)
Toshiki Sugimoto, Hiroshi Tanimoto, Shingo Yoshizawa
Comparator design for linearized statistical flash A-to-D converter. MIXDES (2017)
Shingo Yoshizawa, Hiroshi Tanimoto, Takashi Saito
SC-FDE vs OFDM: Performance comparison in shallow-sea underwater acoustic communication. ISPACS (2016)
Shingo Yoshizawa, Daichi Sasaki, Hiroshi Tanimoto
Power Reduction of Variable Wordlength OFDM Receiver in Time-Varying Fading Channels by Monitoring Subcarrier SNRs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2016)
Akane Tajima, Shingo Yoshizawa, Hiroshi Tanimoto
Performance evaluation of antenna diversity with iterative decoding in OFDM-IDMA systems. DSP (2015)
Hisato Takehata, Toshiki Sugimoto, Hiroshi Tanimoto, Shingo Yoshizawa
FPGA implementation of stochastic flash A-to-D converter and its evaluation. ISCIT (2015)
Shingo Yoshizawa, Mai Nozaki, Hiroshi Tanimoto
VLSI Implementation of an Interference Canceller Using Dual-Frame Processing for OFDM-IDMA Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2015)
Toshiki Sugimoto, Hiroshi Tanimoto, Shingo Yoshizawa
A stochastic flash A-to-D converter with dynamic element matching technique. ISCIT (2015)
Yuji Yokota, Shingo Yoshizawa, Hiroshi Ochi
ASIP implementation of a low complexity iterative BD precoder for MU-MIMO system. ISCIT (2015)
Shun Akada, Shingo Yoshizawa, Hiroshi Tanimoto, Takashi Saito
Experimental evaluation of data selective rake reception for underwater acoustic communication. ISPACS (2015)
Shingo Yoshizawa, Hiroshi Tanimoto
A low power OFDM receiver monitoring subcarrier SNRs in time-varying fading channels. ISCIT (2015)
Nozomi Miyazaki, Shingo Yoshizawa, Yoshikazu Miyanaga
Low-Power Dynamic MIMO Detection for a 4×4 MIMO-OFDM Receiver. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2014)
Ryuta Ishimoto, Shingo Yoshizawa, Hiroshi Tanimoto, Takashi Saito
Evaluation of diversity combining methods for underwater acoustic OFDM communication. ISPACS (2014)
Mai Nozaki, Shingo Yoshizawa, Hiroshi Tanimoto
VLSI design of an interference canceller for QPSK OFDM-IDMA systems. APCCAS (2014)
Kosuke Shimazaki, Shingo Yoshizawa, Yasuyuki Hatakawa, Tomoko Matsumoto, Satoshi Konishi, Yoshikazu Miyanaga
A VLSI design of an arrayed pipelined Tomlinson-Harashima precoder for MU-MIMO systems. APSIPA (2013)
Hiroki Iwaizumi, Shingo Yoshizawa, Yoshikazu Miyanaga
A High-Speed and Low-Energy-Consumption Processor for SVD-MIMO-OFDM Systems. VLSI Design 2013 (2013)
Kosuke Shimazaki, Shingo Yoshizawa, Yasuyuki Hatakawa, Tomoko Matsumoto, Satoshi Konishi, Yoshikazu Miyanaga
A VLSI Design of a Tomlinson-Harashima Precoder for MU-MIMO Systems Using Arrayed Pipelined Processing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2013)
Shingo Yoshizawa, Yoshikazu Miyanaga
Evaluation of Cover and Reflector in Receiver Antennas for SM-MIMO Wireless Communications. J. Electr. Comput. Eng. 2013 (2013)
Shingo Yoshizawa, Yasuyuki Hatakawa, Tomoko Matsumoto, Satoshi Konishi, Yoshikazu Miyanaga
Hardware implementation of an interference canceller for IDMA wireless communications. ISPACS (2013)
Kazi Obaidullah, Constantin Siriteanu, Shingo Yoshizawa, Yoshikazu Miyanaga
Effects of Channel Features on Parameters of Genetic Algorithm for MIMO Detection. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2013)
Yoshikazu Miyanaga, Wataru Takahashi, Shingo Yoshizawa
A Robust Speech Communication into Smart Info-Media System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2013)
Shingo Yoshizawa, Masahiro Sugitani, Yoshikazu Miyanaga
Effectiveness of cover and reflector in receiver antennas for MIMO line-of-sight channels. PIMRC (2013)
Shingo Yoshizawa, Yoshikazu Miyanaga
Design of Area- and Power-Efficient Pipeline FFT Processors for 8x8 MIMO-OFDM Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2012)
Yusaku Kaneta, Shingo Yoshizawa, Shin-ichi Minato, Hiroki Arimura, Yoshikazu Miyanaga
A Dynamically Reconfigurable FPGA-Based Pattern Matching Hardware for Subclasses of Regular Expressions. IEICE Trans. Inf. Syst. (7) (2012)
Xiaonan Nicole Shi, Constantin Siriteanu, Shingo Yoshizawa, Yoshikazu Miyanaga
Realistic Rician fading channel based optimal linear MIMO precoding evaluation. ISCCSP (2012)
Jaeseong Kim, Shingo Yoshizawa, Yoshikazu Miyanaga
Variable wordlength soft-decision Viterbi decoder for power-efficient wireless LAN. Integr. 45 (2) (2012)
Hiroki Iwaizumi, Shingo Yoshizawa, Yoshikazu Miyanaga
A new high-speed and low-power LSI design of SVD-MIMO-OFDM systems. ISCIT (2012)
Jaeseong Kim, Shingo Yoshizawa, Yoshikazu Miyanaga
A low-power MMSE MIMO detector using dynamic voltage wordlength scaling for 4×4 MIMO-OFDM systems. ISCAS (2012)
Kazi Obaidullah, Constantin Siriteanu, Shingo Yoshizawa, Yoshikazu Miyanaga
Evaluation of genetic algorithm-based detection for correlated MIMO fading channels. ISCIT (2011)
Shingo Yoshizawa, Daisuke Nakagawa, Nozomi Miyazaki, Takaya Kaji, Yoshikazu Miyanaga
LSI development of 8×8 single-user MIMO-OFDM for IEEE 802.11ac WLANs. ISCIT (2011)
Shingo Yoshizawa, Atsushi Orikasa, Yoshikazu Miyanaga
An area and power efficient pipeline FFT processor for 8×8 MIMO-OFDM systems. ISCAS (2011)
Nozomi Miyazaki, Shingo Yoshizawa, Yoshikazu Miyanaga
Low-power dynamic MIMO detection for a 4×4 MIMO-OFDM receiver. ISPACS (2011)
Hisayoshi Kano, Shingo Yoshizawa, Takashi Gunji, Shougo Okamoto, Morio Tawarayama, Yoshikazu Miyanaga
Development and Outdoor Evaluation of an Experimental Platform in an 80-MHz Bandwidth 2×2 MIMO-OFDM System in 5.2-GHz Band. IEICE Trans. Inf. Syst. (12) (2011)
Takaya Kaji, Shingo Yoshizawa, Yoshikazu Miyanaga
Development of an ASIP-based singular value decomposition processor in SVD-MIMO systems. ISPACS (2011)
Shingo Yoshizawa, Hirokazu Ikeuchi, Yoshikazu Miyanaga
VLSI Implementation of a Scalable Pipeline MMSE MIMO Detector for a 4×4 MIMO-OFDM Receiver. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2011)
Kazi Obaidullah, Constantin Siriteanu, Shingo Yoshizawa, Yoshikazu Miyanaga
Fading effects on parameter selection in genetic algorithm for MIMO detection. ISPACS (2011)
Jun Takizawa, Takaya Kaji, Shingo Yoshizawa, Takashi Gunji, Morio Tawarayama, Yoshikazu Miyanaga
Development of wireless video transmission equipment by cooperating hardware and software in wideband MIMO-OFDM system. ISPACS (2011)
Xiaonan Nicole Shi, Constantin Siriteanu, Shingo Yoshizawa, Yoshikazu Miyanaga
MIMO precoding performance for correlated and estimated Rician fading. ISCIT (2011)
Yusaku Kaneta, Shingo Yoshizawa, Shin-ichi Minato, Hiroki Arimura, Yoshikazu Miyanaga
Dynamic reconfigurable bit-parallel architecture for large-scale regular expression matching. FPT (2010)
Shingo Yoshizawa, Shinya Odagiri, Yasuhiro Asai, Takashi Gunji, Takashi Saito, Yoshikazu Miyanaga
Development and outdoor evaluation of an experimental platform in an 80-MHz bandwidth 2×2 MIMO-OFDM system at 5.2-GHz band. PIMRC (2010)
Shingo Yoshizawa, Hirokazu Ikeuchi, Yoshikazu Miyanaga
Scalable pipeline architecture of MMSE MIMO detector for 4×4 MIMO-OFDM receiver. ISCAS (2010)
Jaeseong Kim, Shingo Yoshizawa, Yoshikazu Miyanaga
Dynamic wordlength calibration to reduce power dissipation in wireless OFDM systems. APCCAS (2010)
Shingo Yoshizawa, Yoshikazu Miyanaga
VLSI Implementation of a 4×4 MIMO-OFDM transceiver with an 80-MHz Channel Bandwidth. ISCAS (2009)
Chusit Pradabpet, Shingo Yoshizawa, Yoshikazu Miyanaga, Kobchai Dejhan
New PAPR Reduction in an OFDM System Using Hybrid of PTS-CAPPR Methods with GA Coded Side Information Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2009)
Shingo Yoshizawa, Yoshikazu Miyanaga
Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy Dissipation. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2008)
Shingo Yoshizawa, Yasushi Yamauchi, Yoshikazu Miyanaga
VLSI Implementation of a Complete Pipeline MMSE Detector for a 4 x 4 MIMO-OFDM Receiver. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2008)
Chusit Pradabpet, Shingo Yoshizawa, Yoshikazu Miyanaga, Kobchai Dejhan
New PAPR Reduction in OFDM System Using Hybrid of PTS-APPR Methods with Coded Side Information Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2008)
Shingo Yoshizawa, Yasushi Yamauchi, Yoshikazu Miyanaga
A complete pipelined MMSE detection architecture in a 4x4 MIMO-OFDM receiver. ISCAS (2008)
Shingo Yoshizawa, Kazuto Nishi, Yoshikazu Miyanaga
Reconfigurable two-dimensional pipeline FFT processor in OFDM cognitive radio systems. ISCAS (2008)
Shingo Yoshizawa, Yoshikazu Miyanaga
Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy Dissipation. ISCAS (2007)
Takayuki Sugawara, Shingo Yoshizawa, Yoshikazu Miyanaga
Dynamic Reconfigurable Architecture for a Low-Power Despreader in VSF-OFCDM Systems. ISCAS (2007)
Shingo Yoshizawa, Naoya Wada, Noboru Hayasaka, Yoshikazu Miyanaga
Scalable architecture for word HMM-based speech recognition and VLSI implementation in complete system. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2006)
Shingo Yoshizawa, Yoshikazu Miyanaga
Tunable word length architecture for low power wireless OFDM demodulator. ISCAS (2006)
Shingo Yoshizawa, Yoshikazu Miyanaga
VLSI Implementation of a 600-Mbps MIMO-OFDM Wireless Communication System. APCCAS (2006)
Shingo Yoshizawa, Yoshikazu Miyanaga
Tunable Wordlength Architecture for a Low Power Wireless OFDM Demodulator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2006)
Shingo Yoshizawa, Yoshikazu Miyanaga, Hiroshi Ochi, Yoshio Itoh, Nobuo Hataoka, Baiko Sai, Norihisa Takayama, Masaki Hirata
300-Mbps OFDM baseband transceiver for wireless LAN systems. ISCAS (2006)
Naoya Wada, Noboru Hayasaka, Shingo Yoshizawa, Yoshikazu Miyanaga
Direct control on modulation spectrum for noise-robust speech recognition and spectral subtraction. ISCAS (2006)
Yasuyuki Hatakawa, Shingo Yoshizawa, Yoshikazu Miyanaga
Robust VLSI architecture for system-on-chip design and its implementation in Viterbi decoder. ISCAS (1) (2005)
Shingo Yoshizawa, Noboru Hayasaka, Naoya Wada, Yoshikazu Miyanaga
VLSI Architecture for Robust Speech Recognition Systems and its Implementation on a Verification Platform. J. Robotics Mechatronics 17 (4) (2005)
Shingo Yoshizawa, Noboru Hayasaka, Naoya Wada, Yoshikazu Miyanaga
Cepstral gain normalization for noise robust speech recognition. ICASSP (1) (2004)
Shingo Yoshizawa, Naoya Wada, Noboru Hayasaka, Yoshikazu Miyanaga
Scalable architecture for word HMM-based speech recognition. ISCAS (3) (2004)
Shingo Yoshizawa, Noboru Hayasaka, Naoya Wada, Yoshikazu Miyanaga
Cepstral Amplitude Range Normalization for Noise Robust Speech Recognition. IEICE Trans. Inf. Syst. (8) (2004)