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VLSI Implementation of a Scalable Pipeline MMSE MIMO Detector for a 4×4 MIMO-OFDM Receiver.
Shingo Yoshizawa
Hirokazu Ikeuchi
Yoshikazu Miyanaga
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2011)
Keyphrases
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vlsi implementation
mimo ofdm
multiple input multiple output
vlsi architecture
channel estimation
channel state information
mimo systems
fading channels
low power
multipath
fir filters
associative memory
communication systems
filter bank
low complexity
bit error rate
channel capacity
long term evolution