Saroja V. Siddamal

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 11

Top Topics

Data Acquisition

Gate Dielectrics

Top Venues

Publications

Dharmaray Nedalgi, Saroja V. Siddamal, S. S. Kerur
2×VDD IO buffer with 1×VDD devices considering hot-carrier and gate-oxide reliability issues. Integr. 98 (2024)
Dharmaray Nedalgi, Lavanya M. N, Saroja V. Siddamal
Supply Noise and Peak Current Reduction in High-Speed Output Drivers. VLSID (2023)
Dharmaray Nedalgi, Saroja V. Siddamal
Differential receiver with 2 × VDD input signals using 1 × VDD devices. Integr. 87 (2022)
Dharmaray Nedalgi, Saroja V. Siddamal
Mixed-Voltage I/O Buffer Using NMOS Blocking Considering Gate Oxide Reliability. J. Circuits Syst. Comput. 31 (11) (2022)
Dharmaray Nedalgi, Saroja V. Siddamal
$2 \times \text{VDD}$ Tolerant I/O with Considerations of Hot-Carrier Degradation and Gate-Oxide Reliability. APCCAS (2021)
Dharmaray Nedalgi, Saroja V. Siddamal
Novel Gate Tracking and N-well Control Circuit for $2\times \text{VDD}$ Tolerant I/O Buffer. APCCAS (2021)
Dharmaray Nedalgi, Saroja V. Siddamal
High Voltage Receiver Using Low Voltage Devices With Reduced Dead-zone. VLSI Design (2021)
Mandakini Kadam, Saroja V. Siddamal, Shripadraj Annigeri
Design and Implementation of chaotic nondeterministic random seed-based Hybrid True Random Number Generator. VDAT (2020)
Saroja V. Siddamal, Suhas B. Shirol, Shraddha Hiremath, Nalini C. Iyer
Design and Physical Implementation of Mixed Signal Elapsed Time Counter in 0.18 µm CMOS Technology. VDAT (2019)
Sachin Kalburgi, Deven Gupta, Sampath Holi, Rohit Shetty, Shripad Annigeri, Shraddha H, Saroja V. Siddamal, Sujata Kotabagi, Nalini C. Iyer
Ultra Low Power Low Frequency On-chip Oscillator for Elapsed Time Counter. VLSI Design (2019)
Akashaykumar H. Sunagar, Saroja V. Siddamal
Development of Data Acquisition System using non-invasive Hardware and 3D software for Electric all terrain Vehicle. ICACCI (2018)
Narayan V. Sugur, Saroja V. Siddamal, Samba Sivam Vemala
Design and Implementation of High Throughput and Area Efficient Hard Decision Viterbi Decoder in 65nm Technology. VLSI Design (2014)
Saroja V. Siddamal, R. M. Banakar, B. C. Jinaga
Design of High-Speed Floating Point Multiplier. DELTA (2008)