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Samuele Germiniani
ORCID
Publication Activity (10 Years)
Years Active: 2020-2023
Publications (10 Years): 11
Top Topics
Formal Specification
Boolean Expressions
Decision Tree Algorithms
Program Slicing
Top Venues
VLSI-SoC
LATS
DATE
VLSI-SoC (Selected Papers)
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Publications
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Alberto Bosio
,
Samuele Germiniani
,
Graziano Pravadelli
,
Marcello Traiola
Exploiting assertions mining and fault analysis to guide RTL-level approximation.
DATE
(2023)
Samuele Germiniani
,
Graziano Pravadelli
HARM: A Hint-Based Assertion Miner.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
41 (11) (2022)
Samuele Germiniani
,
Graziano Pravadelli
Exploiting clustering and decision-tree algorithms to mine LTL assertions containing non-boolean expressions.
VLSI-SoC
(2022)
Michele Boldo
,
Nicola Bombieri
,
Mirco De Marchi
,
Luca Geretti
,
Samuele Germiniani
,
Graziano Pravadelli
Risk Assessment and Prediction in Human-Robot Interaction Through Assertion Mining and Pose Estimation.
LATS
(2022)
Alberto Bosio
,
Moreno Bragaglio
,
Samuele Germiniani
,
Samuele Mori
,
Graziano Pravadelli
,
Marcello Traiola
Assertion-aware approximate computing design exploration on behavioral models.
LATS
(2022)
Samuele Germiniani
,
Alessandro Danese
,
Graziano Pravadelli
Automatic Generation of Assertions for Detection of Firmware Vulnerabilities Through Alignment of Symbolic Sequences.
IEEE Trans. Emerg. Top. Comput.
10 (2) (2022)
Moreno Bragaglio
,
Nicola Donatelli
,
Samuele Germiniani
,
Graziano Pravadelli
System-level bug explanation through program slicing and instruction clusterization.
VLSI-SoC
(2021)
Stefano Aldegheri
,
Nicola Bombieri
,
Samuele Germiniani
,
Federico Moschin
,
Graziano Pravadelli
A containerized ROS-compliant verification environment for robotic systems.
DATE
(2021)
Moreno Bragaglio
,
Samuele Germiniani
,
Graziano Pravadelli
Exploiting Program Slicing and Instruction Clusterization to Identify the Cause of Faulty Temporal Behaviours at System Level.
VLSI-SoC (Selected Papers)
(2021)
Samuele Germiniani
,
Moreno Bragaglio
,
Graziano Pravadelli
MIST: monitor generation from informal specifications for firmware verification.
VLSI-SOC
(2020)
Samuele Germiniani
,
Moreno Bragaglio
,
Graziano Pravadelli
From Informal Specifications to an ABV Framework for Industrial Firmware Verification.
VLSI-SoC (Selected Papers)
(2020)