S. P. Joy Vasantha Rani

Publication Activity (10 Years)

Years Active: 2004-2022
Publications (10 Years): 8

Top Topics

Iterative Algorithms

Evolvable Hardware

Analog To Digital Converter

Fault Isolation

Top Venues

J. Circuits Syst. Comput.

Int. J. High Perform. Syst. Archit.

Microelectron. J.

Turkish J. Electr. Eng. Comput. Sci.

Publications

S. P. Joy Vasantha Rani, J. R. Lourdu Jennifer, P. Sudhanya
Approximate Multipliers Design Using Approximate Adders for Image Processing Applications. J. Circuits Syst. Comput. 31 (15) (2022)
P. Sudhanya, S. P. Joy Vasantha Rani
Wire-Length and Run-Time Optimization in FPGA Placement Using Hybrid Iterative Algorithms. J. Circuits Syst. Comput. 30 (5) (2021)
Ranjith Chandrasekharan, S. P. Joy Vasantha Rani
Performance analysis of intrinsic embedded evolvable hardware using memetic and genetic algorithms. Int. J. Bio Inspired Comput. 15 (1) (2020)
R. Thangam, S. P. Joy Vasantha Rani
Nonlinear Controller: Voltage Controlled PFC-Based Fuzzy MDPSM Controller with Predictive Input Voltage. J. Circuits Syst. Comput. 29 (13) (2020)
Chandran Ranjith, S. P. Joy Vasantha Rani
A Fast On-Chip Adaptive Genetic Algorithm Processor for Evolutionary FIR Filter Implementation Using Hardware-Software Co-Design. J. Circuits Syst. Comput. 29 (1) (2020)
Senthil Sivakumar, S. P. Joy Vasantha Rani
Efficient Design of ADC BIST with an Analog Ramp Signal Generation and Digital Error Estimation. J. Circuits Syst. Comput. 28 (3) (2019)
Indhumathi Chellaswamy, S. P. Joy Vasantha Rani
Automatic fault isolation and restoration of distribution system using JADE based Multi-Agents. Turkish J. Electr. Eng. Comput. Sci. 27 (3) (2019)
Senthil Sivakumar, S. P. Joy Vasantha Rani
An ADC BIST using on-chip ramp generation and digital ORA. Microelectron. J. 81 (2018)
S. P. Joy Vasantha Rani
Pipelined hardware design of self tuning controller with on-chip parameter estimator. Int. J. High Perform. Syst. Archit. 5 (3) (2015)
J. Britto Pari, S. P. Joy Vasantha Rani
Reconfigurable RNS FIR Filter Using Higher Radix Multiplier. ACITY (3) (2012)
S. P. Joy Vasantha Rani, P. Kanagasabapathy, L. Suganthi
Field Programmable Gate Array based floating point hardware design of recursive k-means clustering algorithm for Radial Basis Function Neural Network. Int. J. Intell. Syst. Technol. Appl. 6 (1/2) (2009)
S. P. Joy Vasantha Rani, P. Kanagasabapathy
Design of Neural Network on FPGA. ESA/VLSI (2004)