Ramaswami Dandapani

Publication Activity (10 Years)

Years Active: 1973-2002
Publications (10 Years): 0

Publications

Dave Stang, Ramaswami Dandapani
An Implementation of IEEE 1149.1 to Avoid Timing Violations and Other Practical In-Compliance Improvements. ITC (2002)
David J. Cheek, Ramaswami Dandapani
Integration of IEEE Std. 1149.1 and Mixed-Signal Test Architectures. ITC (1995)
John R. Wallack, Ramaswami Dandapani
Coverage metrics for functional tests. VTS (1994)
Yunsheng Lu, Weiwei Mao, Ramaswami Dandapani, Ravi K. Gulati
Structure and Metrology for a Single-wire Analog. ITC (1994)
Yunsheng Lu, Ramaswami Dandapani
Hard faults diagnosis in analog circuits using sensitivity analysis. VTS (1993)
V. Chandramouli, Ravi K. Gulati, Ramaswami Dandapani, Deepak K. Goel
Bridging faults and their implication to PLAs. ITC (1990)
Ramaswami Dandapani, Ravi K. Gulati, Deepak K. Goel
Built-in self-test for large embedded CMOS folded PLAs. ICCAD (1988)
Sudhakar M. Reddy, Ramaswami Dandapani
Scan Design Using Standard Flip-Flops. IEEE Des. Test 4 (1) (1987)
Kewal K. Saluja, Ramaswami Dandapani
Testable Design of Single-Output Sequential Machines Using Checking Experiments. IEEE Trans. Computers 35 (7) (1986)
Kewal K. Saluja, Ramaswami Dandapani
An Alternative to Scan Design Methods for Sequential Machines. IEEE Trans. Computers 35 (4) (1986)
Ramaswami Dandapani, Janak H. Patel, Jacob A. Abraham
Design of Test Pattern Generators for Built-In Test. ITC (1984)
Ramaswami Dandapani, Sudhakar M. Reddy
On the Design of Logic Networks with Redundancy and Testability Considerations. IEEE Trans. Computers 23 (11) (1974)
Ramaswami Dandapani
Derivation of Minimal Test Sets for Monotonic Logic Circuits. IEEE Trans. Computers 22 (7) (1973)