Ramachandra Achar

Publication Activity (10 Years)

Years Active: 1995-2023
Publications (10 Years): 13

Top Topics

Cryptographic Algorithms

Transfer Function

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Ahsan Javaid, Ramachandra Achar
PSIJ Transfer Function Response Prediction via NARNET and KBNNs. NEWCAS (2023)
Wai-Kong Lee, Hwajeong Seo, Seong Oun Hwang, Ramachandra Achar, Angshuman Karmakar, Jose Maria Bermudo Mera
DPCrypto: Acceleration of Post-Quantum Cryptography Using Dot-Product Instructions on GPUs. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (9) (2022)
Wai-Kong Lee, Ramachandra Achar
Algorithmic Advancements and a Comparative Investigation of Left and Right Looking Sparse LU Factorization on GPU Platform for Circuit Simulation. IEEE Access 10 (2022)
Muhammed Suhail Illikkal, Jai Narayan Tripathi, Vijender Kumar Sharma, Hitesh Shrimali, Ramachandra Achar
Novel Observations and Physical Insights on PSIJ Behavior in CMOS Chain-of-Inverters. IEEE Access 10 (2022)
Wai-Kong Lee, Hwajeong Seo, Seong Oun Hwang, Angshuman Karmakar, Jose Maria Bermudo Mera, Ramachandra Achar
DPCrypto: Acceleration of Post-quantum Cryptographic Algorithms using Dot-Product Instruction on GPUs. IACR Cryptol. ePrint Arch. 2021 (2021)
Wai-Kong Lee, Ramachandra Achar
GPU-Accelerated Adaptive PCBSO Mode-Based Hybrid RLA for Sparse LU Factorization in Circuit Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (11) (2021)
Srinidhi Ganeshan, Naveen Kumar Elumalai, Ramachandra Achar
A Comparative Study of MAGMA and cuBLAS Libraries for GPU based Vector Fitting. LASCAS (2020)
Wei Pau Kiat, Kai Ming Mok, Wai-Kong Lee, Hock Guan Goh, Ramachandra Achar
An energy efficient FPGA partial reconfiguration based micro-architectural technique for IoT applications. Microprocess. Microsystems 73 (2020)
Jai Narayan Tripathi, Muhammed Suhail Illikkal, Hitesh Shrimali, Ramachandra Achar
A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers. IEEE Access 7 (2019)
Ihsan Erdin, Ramachandra Achar
A Segmentation Algorithm for Capacitively Loaded Planar Resonant Structures. LASCAS (2019)
Wai-Kong Lee, Ramachandra Achar, Michel S. Nakhla
Dynamic GPU Parallel Sparse LU Factorization for Fast Circuit Simulation. IEEE Trans. Very Large Scale Integr. Syst. 26 (11) (2018)
Jai Narayan Tripathi, Ramachandra Achar, Rakesh Malik
Fast Analysis of Time Interval Error in Current-Mode Drivers. IEEE Trans. Very Large Scale Integr. Syst. 26 (2) (2018)
Mina A. Farhan, Michel S. Nakhla, Emad Gad, Ramachandra Achar
Parallel High-Order Envelope-Following Method for Fast Transient Analysis of Highly Oscillatory Circuits. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Douglas Paul, Ramachandra Achar, Michel S. Nakhla, Natalie Nakhla
Addressing Partitioning Issues in Parallel Circuit Simulation. IEEE Trans. Very Large Scale Integr. Syst. 22 (12) (2014)
Douglas Paul, Ramachandra Achar, Michel S. Nakhla, Natalie Nakhla
Efficient parallel scheduler for circuit simulation exploiting binary link formulations. LASCAS (2013)
Yinghong Zhou, Emad Gad, Michel S. Nakhla, Ramachandra Achar
Structural Characterization and Efficient Implementation Techniques for $A$-Stable High-Order Integration Methods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (1) (2012)
Ramachandra Achar, Michel S. Nakhla, Harjot S. Dhindsa, Arvind R. Sridhar, Douglas Paul, Natalie Nakhla
Parallel and Scalable Transient Simulator for Power Grids via Waveform Relaxation (PTS-PWR). IEEE Trans. Very Large Scale Integr. Syst. 19 (2) (2011)
Nick Soveiko, Michel S. Nakhla, Ramachandra Achar
Comparison Study of Performance of Parallel Steady State Solver on Different Computer Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (1) (2010)
Emad Gad, Michel S. Nakhla, Ramachandra Achar, Yinghong Zhou
A-Stable and L-Stable High-Order Integration Methods for Solving Stiff Differential Equations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (9) (2009)
Changzhong Chen, Dharmendra Saraswat, Ramachandra Achar, Emad Gad, Michel S. Nakhla, Mustapha Chérif-Eddine Yagoub
Passivity Compensation Algorithm for Method-of-Characteristics-Based Multiconductor Transmission Line Interconnect Macromodels. IEEE Trans. Very Large Scale Integr. Syst. 17 (8) (2009)
Changzhong Chen, Dharmendra Saraswat, Ramachandra Achar, Emad Gad, Michel S. Nakhla, Mustapha Chérif-Eddine Yagoub
A Robust Algorithm for Passive Reduced-Order Macromodeling of MTLs With FD-PUL Parameters Using Integrated Congruence Transform. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (3) (2008)
Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla
Fast Passivity Verification and Enforcement via Reciprocal Systems for Interconnects With Large Order Macromodels. IEEE Trans. Very Large Scale Integr. Syst. 15 (1) (2007)
Natalie Nakhla, Michel S. Nakhla, Ramachandra Achar
Sparse and passive reduction of massively coupled large multiport interconnects. ICCAD (2007)
Changzhong Chen, Emad Gad, Natalie Nakhla, Ramachandra Achar
Analysis of Frequency-Dependent Interconnects Using Integrated Congruence Transform. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (6) (2007)
Gurpreet Shinh, Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Ihsan Erdin
Efficient and Accurate EMC Analysis of High-Frequency VLSI Subnetworks. VLSI Design (2006)
Praveen Pai, Emad Gad, Ramachandra Achar, Michel S. Nakhla, Roni Khazaka
A Projection-Based Reduction Approach to Computing Sensitivity of Steady-State Response of Nonlinear Circuits. INFORMS J. Comput. 18 (2) (2006)
Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla
Circuit Compatible Macromodeling of High-Speed VLSI Modules Characterized by Scattering Parameters. VLSI Design (2006)
Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla
Accurate and closed-form SPICE compatible passive macromodels for distributed interconnects with frequency dependent parameters. ISCAS (6) (2005)
Emad Gad, Changzhong Chen, Michel S. Nakhla, Ramachandra Achar
Passivity verification in delay-based macromodels of electrical interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2005)
Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla
On passivity enforcement for macromodels of S-parameter based tabulated subnetworks. ISCAS (4) (2005)
Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla
Global Passivity Enforcement Algorithm for Macromodels of Interconnect Subnetworks Characterized by Tabulated Data. IEEE Trans. Very Large Scale Integr. Syst. 13 (7) (2005)
Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Anestis Dounavis
Delay extraction based closed-form SPICE compatible passive macromodels for distributed transmission line interconnects. ASP-DAC (2005)
Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla
Projection Based Fast Passive Compact Macromodeling of High-Speed VLSI Circuits and Interconnects. VLSI Design (2005)
Natalie Nakhla, Anestis Dounavis, Ramachandra Achar, Michel S. Nakhla
Fast sensitivity analysis of transmission line networks. ISCAS (5) (2004)
Praveen Pai, Emad Gad, Ramachandra Achar, Roni Khazaka, Michel S. Nakhla
Computing large-change sensitivity of periodic responses of nonlinear circuits using reduction techniques. ISCAS (5) (2004)
Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla
Passive macromodeling of subnetworks characterized by measured data. ISCAS (3) (2003)
Anestis Dounavis, Ramachandra Achar, Michel S. Nakhla
Passive closed-form time-domain macromodels for on-chip distributed RC interconnects. CICC (2002)
Ramachandra Achar, Michel S. Nakhla
Correction To "simulation of high-speed Interconnects". Proc. IEEE 89 (8) (2001)
Anestis Dounavis, Ramachandra Achar, Michel S. Nakhla
A general class of passive macromodels for efficient sensitivity analysis of high-speed distributed interconnects with nonlinear terminations. ICECS (2001)
Ramachandra Achar, Michel S. Nakhla
Simulation of high-speed interconnects. Proc. IEEE 89 (5) (2001)
Pavan K. Gunupudi, Michel S. Nakhla, Ramachandra Achar
Simulation of high-speed distributed interconnects using Krylov-space techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (7) (2000)
Emad Gad, Anestis Dounavis, Michel S. Nakhla, Ramachandra Achar
Passive model order reduction of multiport distributed interconnects. DAC (2000)
Pavan K. Gunupudi, Michel S. Nakhla, Ramachandra Achar
Multi-point multi-port reduction of high-speed distributed interconnects using Krylov-space techniques. ISCAS (6) (1999)
Ramachandra Achar, Michel S. Nakhla
Efficient simulation of on-chip RF components using model-reduction techniques. ISCAS (2) (1999)
Ramachandra Achar, Michel S. Nakhla, Qi-Jun Zhang
Full-wave analysis of high-speed interconnects using complex frequency hopping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (10) (1998)
Guowu Zheng, Qi-Jun Zhang, Michel S. Nakhla, Ramachandra Achar
An efficient approach for moment-matching simulation of linear subnetworks with measured or tabulated data. ICCAD (1996)
Ramachandra Achar, Michel S. Nakhla, Qi-Jun Zhang
Addressing high frequency effects in VLSI interconnects with full wave model and CFH. ICCAD (1995)