Rajeevan Chandel

Publication Activity (10 Years)

Years Active: 2007-2022
Publications (10 Years): 14

Top Topics

Thresholding Method

Vlsi Architecture

Top Venues

Microelectron. J.

Circuits Syst. Signal Process.

Int. J. Model. Simul. Sci. Comput.

Publications

Ajay Kumar, Rajeevan Chandel, Rohit Dhiman
Proposal and analysis of carbon nanotube based differential multibit through glass vias. Microelectron. J. 126 (2022)
Deepanshu Kaushal, Rajeevan Chandel
Improving the Flare Perturbation Response of Gasket Monopole Antenna for Custom Frequency Solutions. iSES (2022)
Ashish Singh, Rajeevan Chandel, Rohit Dhiman
Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects. Integr. 80 (2021)
Neha Sharma, Rajeevan Chandel
Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS. Int. J. Model. Simul. Sci. Comput. 12 (4) (2021)
Sunil Jadav, Shubham Tayal, Rajeevan Chandel, Munish Vashishath
High speed RLC equivalent RC delay model using normalized asymptotic function for global VLSI interconnects. Microelectron. J. 107 (2021)
Girish Kumar Mekala, Yash Agrawal, Vobulapuram Ramesh Kumar, Rajeevan Chandel
A prominent unified crosstalk model for linear and sub-threshold regions in mixed CNT bundle interconnects. Microelectron. J. 118 (2021)
Yash Agrawal, Girish Kumar Mekala, Rajeevan Chandel
A Unified Delay, Power and Crosstalk Model for Current Mode Signaling Multiwall Carbon Nanotube Interconnects. Circuits Syst. Signal Process. 37 (4) (2018)
Parmjit Singh, Rajeevan Chandel, Neha Sharma
Stability analysis of SRAM cell using CNT and GNR field effect transistors. IC3 (2017)
Girish Kumar Mekala, Yash Agrawal, Rajeevan Chandel
Modelling and performance analysis of dielectric inserted side contact multilayer graphene nanoribbon interconnects. IET Circuits Devices Syst. 11 (3) (2017)
Ramesh Kumar, Rohit Dhiman, Rajeevan Chandel
Performance Analysis of Top-Contact MLGNR Based Interconnects. iNIS (2016)
Sanjay Singh Rajput, Ashish Singh, Ashwani Kumar Chandel, Rajeevan Chandel
Design of Low-Power High-Gain Operational Amplifier for Bio-Medical Applications. ISVLSI (2016)
Rohit Dhiman, Rajeevan Chandel
Dynamic Crosstalk Analysis in Coupled Interconnects for Ultra-Low Power Applications. Circuits Syst. Signal Process. 34 (1) (2015)
Girish Kumar Mekala, Rajeevan Chandel, Yash Agrawal
Timing and Stability Analysis of Carbon Nanotube Interconnects. iNIS (2015)
Yash Agrawal, Rajeevan Chandel, Girish Kumar Mekala
Performance Analysis of Multilayer Graphene Nano-Ribbon in Current-Mode Signaling Interconnect System. iNIS (2015)
Sunil Jadav, Munish Vashistah, Rajeevan Chandel
Carbon Nanotube Based Delay Model For High Speed Energy Efficient on Chip Data Transmission Using: Current Mode Technique. CoRR (2014)
Rohit Dhiman, Rajeevan Chandel
Sub-Threshold Delay and Power Analysis of Complementary Metal-Oxide Semiconductor Buffer Driven Interconnect Load for Ultra Low Power Applications. J. Low Power Electron. 8 (1) (2012)
Sandeep Singh Gill, Rajeevan Chandel, Ashwani Kumar Chandel
Netlist bipartitioning using particle swarm optimisation technique. Int. J. Artif. Intell. Soft Comput. 3 (1) (2012)
T. Alam, Rohit Dhiman, Rajeevan Chandel
Resistive analysis of mixed carbon nanotube bundle interconnect and its comparison with copper interconnect. ICWET (2011)
Kiran K. Chaddha, Rajeevan Chandel
Design and Analysis of a Modified Low Power CMOS Full Adder Using Gate-Diffusion Input Technique. J. Low Power Electron. 6 (4) (2010)
Ashutosh Nandi, Rajeevan Chandel
Design and Analysis of Sub-DT Sub-Domino Logic Circuits for Ultra Low Power Applications. J. Low Power Electron. 6 (4) (2010)
Gargi Khanna, Rajeevan Chandel, Ashwani Kumar Chandel
Impact of skew and jitter on the performance of VLSI interconnects. APCCAS (2010)
Rajeevan Chandel, Sankar Sarkar, Rajendra Prasad Agarwal
An analysis of interconnect delay minimization by low-voltage repeater insertion. Microelectron. J. 38 (4-5) (2007)
Rajeevan Chandel, Sankar Sarkar, Ashwani Kumar Chandel
Investigations on Short-Circuit Power Dissipation in Repeater Loaded VLSI Interconnects. J. Low Power Electron. 3 (3) (2007)