Okihiko Ishizuka

Publication Activity (10 Years)

Years Active: 1977-2010
Publications (10 Years): 0

Publications

Motoi Inaba, Koichi Tanno, Hiroki Tamura, Okihiko Ishizuka
Optimization and Verification of Current-Mode Multiple-Valued Digit ORNS Arithmetic Circuits. IEICE Trans. Inf. Syst. (8) (2010)
Koichi Tanno, Kenya Kondo, Okihiko Ishizuka, Takako Toyama
Combiner-Based MOS OTAs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2005)
Koichi Tanno, Kiminobu Sato, Hisashi Tanaka, Okihiko Ishizuka
Low-Voltage, Low-Distortion and Rail-to-Rail CMOS Sample and Hold Circuit. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2005)
Muneo Kushima, Koichi Tanno, Okihiko Ishizuka
Low-Power and Wide-Input Range Voltage Controlled Linear Variable Resistor Using an FG-MOSFET and Its Application. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2003)
Muneo Kushima, Koichi Tanno, Okihiko Ishizuka
Wide-Input Range Variable Resistor Circuit Using an FG-MOSFET. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Dasong Zhu, Koichi Tanno, Okihiko Ishizuka
Wide Input-Range Four-Quadrant Analog Multiplier Using Floating-Gate MOSFET's. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2003)
Motoi Inaba, Koichi Tanno, Okihiko Ishizuka
Analog Inverter with Neuron-MOS Transistors and Its Application. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2002)
Motoi Inaba, Koichi Tanno, Okihiko Ishizuka
Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits. ISMVL (2002)
Motoi Inaba, Koichi Tanno, Okihiko Ishizuka
Realization of NMAX and NMIN Functions with Multi-Valued Voltage Comparators. ISMVL (2001)
Koichi Tashima, Zheng Tang, Okihiko Ishizuka, Koichi Tanno
An immune network with interactions between B cells for pattern recognition. Systems and Computers in Japan 32 (10) (2001)
Jing Shen, Motoi Inaba, Koichi Tanno, Okihiko Ishizuka
Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors. ISMVL (2000)
Makoto Syuto, Jing Shen, Koichi Tanno, Okihiko Ishizuka
Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Functions. ISMVL (2000)
Jing Shen, Koichi Tanno, Okihiko Ishizuka
Down Literal Circuit with Neuron-MOS Transistors and Its Applications. ISMVL (1999)
Jing Shen, Koichi Tanno, Okihiko Ishizuka, Zheng Tang
Application of Neuron-MOS to Current-Mode Multi-Valued Logic Circuits. ISMVL (1998)
Zheng Tang, Okihiko Ishizuka
A Learning Multiple-Valued Logic Network: Algebra, Algorithm, and Applications. IEEE Trans. Computers 47 (2) (1998)
Okihiko Ishizuka, Akihiro Ohta, Koichi Tanno, Zheng Tang, Dwi Handoko
VLSI Design of a Quaternary Multiplier with Direct Generation of Partial Products. ISMVL (1997)
Zheng Tang, Takayuki Yamaguchi, Koichi Tashima, Okihiko Ishizuka, Koichi Tanno
Multiple-Valued Immune Network Model and Its Simulations. ISMVL (1997)
Zheng Tang, Okihiko Ishizuka, Koichi Tanno
Learning Multiple-Valued Logic Networks Based on Back Propagation. ISMVL (1995)
Zheng Tang, Yuichi Shirata, Okihiko Ishizuka, Koichi Tanno
A Self-Calibrating A/D Converter Using T-Model Neural Network. ISCAS (1995)
Qixin Cao, Okihiko Ishizuka, Zheng Tang, Hiroki Matsumoto
Algorithm and Implementation of a Learning Multiple-Valued Logic Network. ISMVL (1993)
Zheng Tang, Okihiko Ishizuka, Qixin Cao, Hiroki Matsumoto
Algebraic Properties of a Learning Multiple-Valued Logic Network. ISMVL (1993)
Okihiko Ishizuka, Hiroshi Takarabe, Zheng Tang, Hiroki Matsumoto
Synthesis of Current-Mode Pass Transistor Networks. ISMVL (1991)
Okihiko Ishizuka, Zheng Tang, Hiroki Matsumoto
On Design of Multiple-Valued Static Random-Access-Memory. ISMVL (1990)
Okihiko Ishizuka
On Multivalued Multithreshold Networks Composed of Conventional Threshold Elements. IEEE Trans. Computers 26 (12) (1977)