Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits.

Motoi Inaba Koichi Tanno Okihiko Ishizuka

Published in: ISMVL (2002)

Keyphrases

flip flops
multi valued
power dissipation
cmos technology
multiple input
power consumption
single valued
logic synthesis
normal form
low power
boolean functions
master slave
image processing
velocity field