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Low-Voltage, Low-Distortion and Rail-to-Rail CMOS Sample and Hold Circuit.

Koichi TannoKiminobu SatoHisashi TanakaOkihiko Ishizuka
Published in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2005)
Keyphrases
  • low voltage
  • high speed
  • cmos technology
  • low power
  • design considerations
  • power line
  • random access memory
  • power management
  • real time
  • power dissipation
  • low cost