Nan Wang

Publication Activity (10 Years)

Years Active: 2013-2023
Publications (10 Years): 11

Top Topics

Design Space Exploration

Resource Constrained

Weighted Tardiness

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Pengyu Wang, Hongqing Zhu, Han Zhang, Nan Wang
M-CBN: Manifold constrained joint image dehazing and super-resolution based on chord boosting network. Pattern Recognit. 135 (2023)
Pengyu Wang, Hongqing Zhu, Hui Huang, Han Zhang, Nan Wang
TMS-GAN: A Twofold Multi-Scale Generative Adversarial Network for Single Image Dehazing. IEEE Trans. Circuits Syst. Video Technol. 32 (5) (2022)
Manting Yao, Weina Yuan, Nan Wang, Zeyu Zhang, Yuan Qiu, Yichuan Liu
SS3: Security-Aware Vendor-Constrained Task Scheduling for Heterogeneous Multiprocessor System-on-Chips. ICNSC (2020)
Nan Wang, Song Chen, Zhiyuan Ma, Xiaofeng Ling, Yu Zhu
Integrating operation scheduling and binding for functional unit power-gating in high-level synthesis. Integr. 65 (2019)
Nan Wang, Manting Yao, Dongxu Jiang, Song Chen, Yu Zhu
Security-Driven Task Scheduling for Multiprocessor System-on-Chips with Performance Constraints. ISVLSI (2018)
Nan Wang, Song Chen, Jianmo Ni, Xiaofeng Ling, Yu Zhu
Security-Aware Task Scheduling Using Untrusted Components in High-Level Synthesis. IEEE Access 6 (2018)
Nan Wang, Wei Zhong, Song Chen, Zhiyuan Ma, Xiaofeng Ling, Yu Zhu
Power-gating-aware scheduling with effective hardware resources optimization. Integr. 61 (2018)
Xiaofeng Ling, Nan Wang
A Flexible Broadband Single RF Architecture Based on Time-Modulated Array. CSPS (3) (2018)
Cong Hao, Jianmo Ni, Nan Wang, Takeshi Yoshimura
Interconnection Allocation Between Functional Units and Registers in High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 25 (3) (2017)
Cong Hao, Nan Wang, Takeshi Yoshimura
in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (12) (2017)
Nan Wang, Wei Zhong, Cong Hao, Song Chen, Takeshi Yoshimura, Yu Zhu
Leakage-Power-Aware Scheduling With Dual-Threshold Voltage Design. IEEE Trans. Very Large Scale Integr. Syst. 24 (10) (2016)
Jianmo Ni, Nan Wang, Takeshi Yoshimura
Tabu search based multiple voltage scheduling under both timing and resource constraints. ISQED (2015)
Jianmo Ni, Cong Hao, Nan Wang, Qian Ai, Takeshi Yoshimura
Primal-dual method based simultaneous functional unit and register binding. ASICON (2015)
Nan Wang, Song Chen, Cong Hao, Haoran Zhang, Takeshi Yoshimura
Leakage Power Aware Scheduling in High-Level Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2014)
Nan Wang, Song Chen, Wei Zhong, Nan Liu, Takeshi Yoshimura
Mobility Overlap-Removal-Based Leakage Power and Register-Aware Scheduling in High-Level Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (8) (2014)
Nan Wang, Song Chen, Yuhuan Sun, Takeshi Yoshimura
Mobility overlap-removal based leakage power aware scheduling in high-level synthesis. ISCAS (2013)
Cong Hao, Nan Wang, Song Chen, Takeshi Yoshimura, Min-You Wu
Interconnection allocation between functional units and registers in High-Level Synthesis. ASICON (2013)
Nan Wang, Cong Hao, Nan Liu, Haoran Zhang, Takeshi Yoshimura
Timing and resource constrained leakage power aware scheduling in high-level synthesis. ASICON (2013)
Haoran Zhang, Cong Hao, Nan Wang, Song Chen, Takeshi Yoshimura
Power and resource aware scheduling with multiple voltages. ASICON (2013)
Nan Wang, Song Chen, Takeshi Yoshimura
Min-cut based leakage power aware scheduling in high-level synthesis. ISQED (2013)