Mojtaba Valinataj

Publication Activity (10 Years)

Years Active: 2007-2023
Publications (10 Years): 12

Top Topics

Classical Logic

Interconnection Networks

Resource Sharing

Error Detection

Top Venues

Microelectron. J.

Microprocess. Microsystems

Inteligencia Artif.

Publications

Zahra Yazdanian Amiri, Mojtaba Valinataj
High-speed binary coded decimal digit multipliers with multiple error detection. Integr. 93 (2023)
Mojtaba Valinataj, Axel Jantsch
Hierarchical multipliers: A framework for high-speed multiple error detecting architectures. Microelectron. J. 125 (2022)
Roya Rahimi Disfani, Nima TaheriNejad, Mojtaba Valinataj
Operational Conditions Analysis for Memristive Stateful Logics - A Study on IMPLY and TMSL. NEWCAS (2022)
Maytham Allahi Rudposhti, Mojtaba Valinataj
High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic. Integr. 79 (2021)
Mojtaba Valinataj, Zahra Yazdanian Amiri
Comments on "Improved designs of digit-by-digit decimal multiplier". Integr. 76 (2021)
Sajjad Rostami-Sani, Mojtaba Valinataj, Saeideh Alinezhad Chamazcoti
Parloom: A New Low-Power Set-Associative Instruction Cache Architecture Utilizing Enhanced Counting Bloom Filter and Partial Tags. J. Circuits Syst. Comput. 28 (12) (2019)
Hamid Jazayeriy, Sahar Bakhtar, Mojtaba Valinataj
aPaRT: A Fast Meta-Heuristic Algorithm using Path-Relinking and Tabu Search for Allocating Machines to Operations in FJSP Problem. Inteligencia Artif. 21 (61) (2018)
Mojtaba Valinataj, Abbas Mohammadnezhad, Jari Nurmi
A low-cost high-speed self-checking carry select adder with multiple-fault detection. Microelectron. J. 81 (2018)
Mojtaba Valinataj
Novel parity-preserving reversible logic array multipliers. J. Supercomput. 73 (11) (2017)
Mostafa Shahiri, Mojtaba Valinataj, Amir M. Rahmani
A reliable and high-performance Network-on-Chip router through decoupled resource sharing. HPCS (2016)
Mojtaba Valinataj, Mostafa Shahiri
A low-cost, fault-tolerant and high-performance router architecture for on-chip networks. Microprocess. Microsystems 45 (2016)
Mojtaba Valinataj, Mahboobeh Mirshekar, Hamid Jazayeri
Novel low-cost and fault-tolerant reversible logic adders. Comput. Electr. Eng. 53 (2016)
Mojtaba Valinataj
Fault-tolerant carry look-ahead adder architectures robust to multiple simultaneous errors. Microelectron. Reliab. 55 (12) (2015)
Mojtaba Valinataj
A novel self-checking carry lookahead adder with multiple error detection/correction. Microprocess. Microsystems 38 (8) (2014)
Mojtaba Valinataj, Pasi Liljeberg, Juha Plosila
Enhanced fault-tolerant Network-on-Chip architecture using hierarchical agents. DDECS (2013)
Mojtaba Valinataj
Evaluation of Fault-Tolerant Routing Methods for NoC Architectures. DSD (2011)
Mojtaba Valinataj, Pasi Liljeberg, Juha Plosila
A fault-tolerant and hierarchical routing algorithm for NoC architectures. NORCHIP (2011)
Mojtaba Valinataj, Siamak Mohammadi
A fault-aware, reconfigurable and adaptive routing algorithm for NoC applications. VLSI-SoC (2010)
Mojtaba Valinataj, Siamak Mohammadi, Juha Plosila, Pasi Liljeberg
A fault-tolerant and congestion-aware routing algorithm for Networks-on-Chip. DDECS (2010)
Mojtaba Valinataj, Siamak Mohammadi, Saeed Safari
Inherent reliability evaluation of Networks-on-Chip based on analytical models. SoC (2008)
Mojtaba Valinataj, Saeed Safari
Fault Tolerant Arithmetic Operations with Multiple Error Detection and Correction. DFT (2007)