Masahiro Sowa

Publication Activity (10 Years)

Years Active: 1982-2012
Publications (10 Years): 0

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Duc-Hung Le, Katsumi Inoue, Masahiro Sowa, Cong-Kha Pham
An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2012)
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
Compiling for Reduced Bit-Width Queue Processors. J. Signal Process. Syst. 59 (1) (2010)
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
Efficient compilation for queue size constrained queue processors. Parallel Comput. 35 (4) (2009)
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
Compiler Support for Code Size Reduction Using a Queue-Based Processor. Trans. High Perform. Embed. Archit. Compil. 2 (2009)
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
Design and implementation of a queue compiler. Microprocess. Microsystems 33 (2) (2009)
Ben A. Abderazek, Arquimedes Canedo, Tsutomu Yoshinaga, Masahiro Sowa
The QC-2 parallel Queue processor architecture. J. Parallel Distributed Comput. 68 (2) (2008)
Arquimedes Canedo, Masahiro Sowa, Ben A. Abderazek
Quantitative Evaluation of Common Subexpression Elimination on Queue Machines. ISPAN (2008)
Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa
Dual-execution mode processor architecture. J. Supercomput. 44 (2) (2008)
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
A new code generation algorithm for 2-offset producer order queue computation model. Comput. Lang. Syst. Struct. 34 (4) (2008)
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model. EUC (2007)
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
Queue Register File Optimization Algorithm for QueueCore Processor. SBAC-PAD (2007)
Yuki Nakanishi, Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
Optimizing Reaching Definitions Overhead in Queue Processors. J. Convergence Inf. Technol. 2 (4) (2007)
Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa
Dual-Execution Mode Processor Architecture For Embedded Applications. J. Mobile Multimedia 3 (4) (2007)
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
New Code Generation Algorithm for QueueCore - An Embedded Processor with High ILP. PDCAT (2007)
Ben A. Abderazek, Mushfiquzzaman Akanda, Tsutomu Yoshinaga, Masahiro Sowa
Mathematical Model for Multiobjective Synthesis of NoC Architectures. ICPP Workshops (2007)
Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa
Scalable Core-Based Methodology and Synthesizable Core for Systematic Design. ICPP Workshops (2006)
Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa
Design and architecture for an embedded 32-bit QueueCore. J. Embed. Comput. 2 (2) (2006)
Ta Quoc Viet, Tsutomu Yoshinaga, Ben A. Abderazek, Masahiro Sowa
Construction of Hybrid MPI-OpenMP Solutions for SMP Clusters. Inf. Media Technol. 1 (1) (2006)
Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa
On the Design of a Dual-Execution Modes Processor: Architecture and Preliminary Evaluation. ISPA Workshops (2006)
Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa
High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core. J. Supercomput. 38 (1) (2006)
Md. Musfiquzzaman Akanda, Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa
An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture. EUC (2005)
Masahiro Sowa, Ben A. Abderazek, Tsutomu Yoshinaga
Parallel Queue Processor Architecture Based on Produced Order Computation Model. J. Supercomput. 32 (3) (2005)
Ben A. Abderazek, Sotaro Kawata, Tsutomu Yoshinaga, Masahiro Sowa
Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core. EUC (2005)
Ben A. Abderazek, Soichi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa
On the Design of a Register Queue Based Processor Architecture (FaRM-rq). ISPA (2003)
Kirilka Nikolova, Masahiro Sowa
Compiler-Controlled Parallelism-Independent Scheduling Method for Cluster Computing Systems. HPCS (2002)
Kirilka Nikolova, Sou Pei You, Masahiro Sowa
Compiler-Controlled Parallelism-Independent Scheduling for Parallel and Distributed Systems. PARA (2002)
Masahiro Sowa, Ben A. Abderazek, Soichi Shigeta, Kirilka Nikolova, Tsutomu Yoshinaga
Proposal and Design of a Parallel Queue Processor Architecture (PQP). IASTED PDCS (2002)
Soichi Shigeta, Kentaro Shimizu, Masahiro Sowa
Access route control by an extended key/lock scheme. Comput. Syst. Sci. Eng. 16 (5) (2001)
Shusuke Okamoto, Masahiro Sowa
Intruction Fetch Mechanism for PN-Superscalar. PDPTA (1997)
Mitsuaki Nakasumi, Shusuke Okamoto, Masahiro Sowa
Program Controlled Cache Memory on Parallel Computer. PDPTA (1997)
Shusuke Okamoto, Masahiro Sowa
Hybrid Processor Based on VLIW and PN-Superscalar. PDPTA (1996)
Takaya Arita, Hiromitsu Takagi, Masahiro Sowa
V++: An Instruction-Restructurable Processor Architecture. HICSS (1) (1994)
Hiromitsu Takagi, Takaya Arita, Masahiro Sowa
A static processor-scheduling algorithm resistive to dynamic fluctuation of execution timing. Systems and Computers in Japan 24 (8) (1993)
Komei Kato, Takaya Arita, Masahiro Sowa
Delayed instruction execution on a long instruction word (LIW) computer. Systems and Computers in Japan 23 (14) (1992)
Takaya Arita, Hiroaki Ito, Masahiro Sowa
Performance of the PN superscalar processor as estimated by simulation. Systems and Computers in Japan 23 (14) (1992)
Takaya Arita, Masahiro Sowa
High Speed Synchronization for a Statically Scheduled Superscalar Processor. Int. J. High Speed Comput. 3 (1) (1991)
Masahiro Sowa, Takaya Arita, Tadaaki Kawamura, Hiromitsu Takagi
Parallel execution on the function-partitioned processor with multiple instruction streams. Systems and Computers in Japan 22 (4) (1991)
Masahiro Sowa, Akitoshi Kamimura
Performance of a simulated dataflow computer DFNDR-2. Systems and Computers in Japan 18 (6) (1987)
T. Smigelski, Tadao Murata, Masahiro Sowa
A Timed Petri Net Model and Simulation of a Dataflow Computer. PNPM (1985)
Masahiro Sowa, Tadao Murata
A Data Flow Computer Architecture with Program and Token Memories. IEEE Trans. Computers 31 (9) (1982)