Ben A. Abderazek

Publication Activity (10 Years)

Years Active: 2002-2010
Publications (10 Years): 0

Publications

Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
Compiling for Reduced Bit-Width Queue Processors. J. Signal Process. Syst. 59 (1) (2010)
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
Efficient compilation for queue size constrained queue processors. Parallel Comput. 35 (4) (2009)
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
Compiler Support for Code Size Reduction Using a Queue-Based Processor. Trans. High Perform. Embed. Archit. Compil. 2 (2009)
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
Design and implementation of a queue compiler. Microprocess. Microsystems 33 (2) (2009)
Ben A. Abderazek, Arquimedes Canedo, Tsutomu Yoshinaga, Masahiro Sowa
The QC-2 parallel Queue processor architecture. J. Parallel Distributed Comput. 68 (2) (2008)
Hiroki Hoshino, Ben A. Abderazek, Kenichi Kuroda
Advanced Optimization and Design Issues of a 32-Bit Embedded Processor Based on Produced Order Queue Computation Model. EUC (1) (2008)
Arquimedes Canedo, Masahiro Sowa, Ben A. Abderazek
Quantitative Evaluation of Common Subexpression Elimination on Queue Machines. ISPAN (2008)
Taichi Maekawa, Ben A. Abderazek, Kenichi Kuroda
Single Instruction Dual-Execution Model Processor Architecture. EUC (1) (2008)
Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa
Dual-execution mode processor architecture. J. Supercomput. 44 (2) (2008)
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
A new code generation algorithm for 2-offset producer order queue computation model. Comput. Lang. Syst. Struct. 34 (4) (2008)
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model. EUC (2007)
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
Queue Register File Optimization Algorithm for QueueCore Processor. SBAC-PAD (2007)
Yuki Nakanishi, Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
Optimizing Reaching Definitions Overhead in Queue Processors. J. Convergence Inf. Technol. 2 (4) (2007)
Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa
Dual-Execution Mode Processor Architecture For Embedded Applications. J. Mobile Multimedia 3 (4) (2007)
Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa
New Code Generation Algorithm for QueueCore - An Embedded Processor with High ILP. PDCAT (2007)
Ben A. Abderazek, Mushfiquzzaman Akanda, Tsutomu Yoshinaga, Masahiro Sowa
Mathematical Model for Multiobjective Synthesis of NoC Architectures. ICPP Workshops (2007)
Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa
Scalable Core-Based Methodology and Synthesizable Core for Systematic Design. ICPP Workshops (2006)
Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa
Design and architecture for an embedded 32-bit QueueCore. J. Embed. Comput. 2 (2) (2006)
Ta Quoc Viet, Tsutomu Yoshinaga, Ben A. Abderazek, Masahiro Sowa
Construction of Hybrid MPI-OpenMP Solutions for SMP Clusters. Inf. Media Technol. 1 (1) (2006)
Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa
On the Design of a Dual-Execution Modes Processor: Architecture and Preliminary Evaluation. ISPA Workshops (2006)
Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa
High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core. J. Supercomput. 38 (1) (2006)
Md. Musfiquzzaman Akanda, Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa
An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture. EUC (2005)
Masahiro Sowa, Ben A. Abderazek, Tsutomu Yoshinaga
Parallel Queue Processor Architecture Based on Produced Order Computation Model. J. Supercomput. 32 (3) (2005)
Ben A. Abderazek, Sotaro Kawata, Tsutomu Yoshinaga, Masahiro Sowa
Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core. EUC (2005)
Ben A. Abderazek, Soichi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa
On the Design of a Register Queue Based Processor Architecture (FaRM-rq). ISPA (2003)
Masahiro Sowa, Ben A. Abderazek, Soichi Shigeta, Kirilka Nikolova, Tsutomu Yoshinaga
Proposal and Design of a Parallel Queue Processor Architecture (PQP). IASTED PDCS (2002)