High Speed Synchronization for a Statically Scheduled Superscalar Processor.

Takaya Arita Masahiro Sowa

Published in: Int. J. High Speed Comput. (1991)

Keyphrases

high speed
instruction set
low power
computer architecture
real time
high speed networks
scheduling problem
frame rate
multithreading
arrival times
highly parallel
phase locked
single chip
information systems