V++: An Instruction-Restructurable Processor Architecture.
Takaya AritaHiromitsu TakagiMasahiro SowaPublished in: HICSS (1) (1994)
Keyphrases
- instruction set
- level parallelism
- memory hierarchy
- floating point
- software architecture
- management system
- embedded systems
- multi processor
- computer architecture
- parallel architecture
- high speed
- parallel processing
- multiprocessor systems
- multi core processors
- memory access
- application specific
- real time
- computation intensive
- memory management
- multimedia