Mamidala Jagadesh Kumar

Publication Activity (10 Years)

Years Active: 2002-2020
Publications (10 Years): 4

Top Topics

Multimedia Content Analysis

Comprehensive Analysis

Simulation Study

Top Venues

IET Circuits Devices Syst.

Publications

Aakash Kumar Jain, Mamidala Jagadesh Kumar
Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study. IEEE Access 8 (2020)
Shubham Sahay, Mamidala Jagadesh Kumar
Comprehensive Analysis of Gate-Induced Drain Leakage in Emerging FET Architectures: Nanotube FETs Versus Nanowire FETs. IEEE Access 5 (2017)
Sindhu Ramaswamy, Mamidala Jagadesh Kumar
Double gate symmetric tunnel FET: investigation and analysis. IET Circuits Devices Syst. 11 (4) (2017)
Rajat Vishnoi, Pratyush Panday, Mamidala Jagadesh Kumar
DC Drain Current Model for Tunnel FETs Considering Source and Drain Depletion Regions. VLSI Design (2017)
Tarun Kumar Agarwal, Mamidala Jagadesh Kumar
Modeling of Partially Depleted SOI DEMOSFETs with a Sub-circuit Utilizing the HiSIM-HV Compact Model. VLSI Design (2012)
Radhakrishnan Sithanandam, Mamidala Jagadesh Kumar
A New Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Applications. VLSI Design (2010)
Mamidala Jagadesh Kumar, Vivek Venkataraman, Susheel Nawal
Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Analog Circuit Simulation. VLSI Design (2007)
Mamidala Jagadesh Kumar, Vinod Parihar
A New Surface Accumulation Layer Transistor(SALTran) Concept for Current Gain Enhancement in Bipolar Transistors. VLSI Design (2004)
G. Venkateshwar Reddy, Mamidala Jagadesh Kumar
Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study. Microelectron. J. 35 (9) (2004)
Mamidala Jagadesh Kumar, C. Linga Reddy
2D-simulation and analysis of lateral SiC N-emitter SiGe P-base Schottky metal-collector (NPM) HBT on SOI. Microelectron. Reliab. 43 (7) (2003)
Mamidala Jagadesh Kumar, D. Venkateshrao
A New Lateral SiGe-Base PNM Schottky Collector Bipolar Transistor on SOI for Non-saturating VLSI Logic Design. VLSI Design (2003)
Mamidala Jagadesh Kumar, Vikram Verma
Elimination of bipolar induced drain breakdown and single transistor latch in submicron PD SOI MOSFET. IEEE Trans. Reliab. 51 (3) (2002)