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Mahendra Sakare
ORCID
Publication Activity (10 Years)
Years Active: 2011-2024
Publications (10 Years): 14
Top Topics
Flip Flops
Associative Memory
Micron Cmos
Neural Network
Top Venues
MWSCAS
IEEE Trans. Circuits Syst. II Express Briefs
VLSI Design
CoRR
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Publications
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Sahibia Kaur Vohra
,
Sherin A. Thomas
,
Mahendra Sakare
,
Devarshi Mrinal Das
Circuit implementation of on-chip trainable spiking neural network using CMOS based memristive STDP synapses and LIF neurons.
Integr.
95 (2024)
Sahibia Kaur Vohra
,
Alex P. James
,
Mahendra Sakare
,
Devarshi Mrinal Das
Analysing Mismatch effect of CMOS Neurons in Spiking Neural Network with Winner-take-all Mechanism.
NorCAS
(2023)
Mayank Kumar Singh
,
Puneet Singh
,
Upendra Chichhula
,
Hirensh Mehra
,
Devarshi Mrinal Das
,
Mahendra Sakare
A PRBS Generator Using Merged XOR-D Flip-Flop as Building Blocks.
Circuits Syst. Signal Process.
42 (11) (2023)
Sahibia Kaur Vohra
,
Sherin A. Thomas
,
Shivdeep
,
Mahendra Sakare
,
Devarshi Mrinal Das
Full CMOS Circuit for Brain-Inspired Associative Memory With On-Chip Trainable Memristive STDP Synapse.
IEEE Trans. Very Large Scale Integr. Syst.
31 (7) (2023)
Mayank Kumar Singh
,
Puneet Singh
,
Devarshi Mrinal Das
,
Mahendra Sakare
A Low Power Differential Delay Cell without Cross-Coupled Latch for Ring VCO.
PRIME
(2023)
Sahibia Kaur Vohra
,
Sherin A. Thomas
,
Mahendra Sakare
,
Devarshi Mrinal Das
CMOS Circuit Implementation of Spiking Neural Network for Pattern Recognition Using On-chip Unsupervised STDP Learning.
CoRR
(2022)
Mayank Kumar Singh
,
Puneet Singh
,
Devarshi Mrinal Das
,
Mahendra Sakare
-1 PRBS generator using Exclusive-OR gate merged D flip-flops.
MWSCAS
(2021)
Sahibia Kaur Vohra
,
Sherin A. Thomas
,
Mahendra Sakare
,
Devarshi Mrinal Das
Analytical Modelling of a CMOS Inter Spike Interval Decoder for Resistive Crossbar based Brain Inspired Computing.
VDAT
(2021)
Sahibia Kaur Vohra
,
Sherin Thomas
,
Mahendra Sakare
,
Devarshi Mrinal Das
Full CMOS Implementation of Bidirectional Associative Memory Neural Network with Analog Memristive Synapse.
MWSCAS
(2021)
Puneet Singh
,
Mayank Kumar Singh
,
Vinayak Gopal Hande
,
Mahendra Sakare
Design of a PRBS generator and a serializer using active inductor employed CML latch.
MWSCAS
(2021)
Mahendra Sakare
A Power and Area Efficient Architecture of a PRBS Generator With Multiple Outputs.
IEEE Trans. Circuits Syst. II Express Briefs
(8) (2017)
Mahendra Sakare
,
Sadhu Pavan Kumar
,
Shalabh Gupta
Bandwidth Enhancement of Flip-Flops Using Feedback for High-Speed Integrated Circuits.
IEEE Trans. Circuits Syst. II Express Briefs
(8) (2016)
Pragya Maheshwari
,
Suhas Kaushik
,
Mahendra Sakare
,
Shalabh Gupta
A 12.5 Gbps One-Fifth Rate CDR Incorporating a Novel Sampler Based Phase Detector and a DFE.
VLSI Design
(2016)
Mahendra Sakare
A Quarter-Rate 27-1 Pseudo-Random Binary Sequence Generator Using Interleaved Architecture.
VLSI Design
(2016)
Mahendra Sakare
,
Shalabh Gupta
A high-speed PRBS generator using flip-flops employing feedback for distributed equalization.
ISCAS
(2014)
Mahendra Sakare
,
Mohit Singh
,
Shalabh Gupta
A 4 × 20 Gb/s 29-1 PRBS Generator for Testing a High-Speed DAC in 90nm CMOS Technology.
VDAT
(2012)
Mohit Singh
,
Mahendra Sakare
,
Shalabh Gupta
Testing of high-speed DACs using PRBS generation with "Alternate-Bit-Tapping".
DATE
(2011)