Liqiang Lu

Publication Activity (10 Years)

Years Active: 2017-2024
Publications (10 Years): 30

Top Topics

Reconfigurable Architecture

Topological Features

Convolutional Neural Networks

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Siwei Tan, Debin Xiang, Liqiang Lu, Junlin Lu, Qiuping Jiang, Mingshuai Chen, Jianwei Yin
MorphQPV: Exploiting Isomorphism in Quantum Programs to Facilitate Confident Verification. ASPLOS (3) (2024)
Liqiang Lu, Zizhang Luo, Size Zheng, Jieming Yin, Jason Cong, Yun Liang, Jianwei Yin
Rubick: A Unified Infrastructure for Analyzing, Exploring, and Implementing Spatial Architectures via Dataflow Decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (4) (2024)
Siwei Tan, Liqiang Lu, Hanyu Zhang, Jia Yu, Congliang Lang, Yongheng Shang, Xinkui Zhao, Mingshuai Chen, Yun Liang, Jianwei Yin
QuFEM: Fast and Accurate Quantum Readout Calibration Using the Finite Element Method. ASPLOS (2) (2024)
Siwei Tan, Congliang Lang, Liang Xiang, Shudi Wang, Xinghui Jia, Ziqi Tan, Tingting Li, Jieming Yin, Yongheng Shang, Andre Python, Liqiang Lu, Jianwei Yin
QuCT: A Framework for Analyzing Quantum Circuit by Extracting Contextual and Topological Features. MICRO (2023)
Wuwei Tian, Xinghui Jia, Siwei Tan, Zixuan Song, Liqiang Lu, Jianwei Yin
QPulseLib: Accelerating the Pulse Generation of Quantum Circuit with Reusable Patterns. ICCAD (2023)
Zizhang Luo, Liqiang Lu, Size Zheng, Jieming Yin, Jason Cong, Jianwei Yin, Yun Liang
Rubick: A Synthesis Framework for Spatial Architectures via Dataflow Decomposition. DAC (2023)
Qi Liu, Mo Sun, Jie Sun, Liqiang Lu, Jieru Zhao, Zeke Wang
SSiMD: Supporting Six Signed Multiplications in a DSP Block for Low-Precision CNN on FPGAs. ICFPT (2023)
Siwei Tan, Mingqian Yu, Andre Python, Yongheng Shang, Tingting Li, Liqiang Lu, Jianwei Yin
HyQSAT: A Hybrid Approach for 3-SAT Problems by Integrating Quantum Annealer with CDCL. HPCA (2023)
Zizhang Luo, Liqiang Lu, Yicheng Jin, Liancheng Jia, Yun Liang
Calabash: Accelerating Attention Using a Systolic Array Chain on FPGAs. FPL (2023)
Liancheng Jia, Zizhang Luo, Liqiang Lu, Yun Liang
Automatic Generation of Spatial Accelerator for Tensor Algebra. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (6) (2023)
Liqiang Lu, Yun Liang
Morphling: A Reconfigurable Architecture for Tensor Computation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Size Zheng, Renze Chen, Anjiang Wei, Yicheng Jin, Qin Han, Liqiang Lu, Bingyang Wu, Xiuhong Li, Shengen Yan, Yun Liang
AMOS: enabling automatic mapping for tensor computations on spatial accelerators with hardware abstraction. ISCA (2022)
Yun Liang, Liqiang Lu, Yicheng Jin, Jiaming Xie, Ruirui Huang, Jiansong Zhang, Wei Lin
An Efficient Hardware Design for Accelerating Sparse CNNs With NAS-Based Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (3) (2022)
Yun Liang, Qingcheng Xiao, Liqiang Lu, Jiaming Xie
FCNNLib: A Flexible Convolution Algorithm Library for Deep Learning on FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (8) (2022)
Liancheng Jia, Zizhang Luo, Liqiang Lu, Yun Liang
TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebra. DAC (2021)
Liancheng Jia, Zizhang Luo, Liqiang Lu, Yun Liang
TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebra. CoRR (2021)
Liqiang Lu, Naiqing Guan, Yuyue Wang, Liancheng Jia, Zizhang Luo, Jieming Yin, Jason Cong, Yun Liang
TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation. ISCA (2021)
Liqiang Lu, Naiqing Guan, Yuyue Wang, Liancheng Jia, Zizhang Luo, Jieming Yin, Jason Cong, Yun Liang
TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation. CoRR (2021)
Liqiang Lu, Yicheng Jin, Hangrui Bi, Zizhang Luo, Peng Li, Tao Wang, Yun Liang
Sanger: A Co-Design Framework for Enabling Sparse Attention using Reconfigurable Architecture. MICRO (2021)
Liancheng Jia, Zizhang Luo, Liqiang Lu, Yun Liang
Analyzing the Design Space of Spatial Tensor Accelerators on FPGAs. ISVLSI (2021)
Yun Liang, Liqiang Lu, Jiaming Xie
OMNI: A Framework for Integrating Hardware and Software Optimizations for Sparse CNNs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (8) (2021)
Liancheng Jia, Liqiang Lu, Xuechao Wei, Yun Liang
Generating Systolic Array Accelerators With Reusable Blocks. IEEE Micro 40 (4) (2020)
Qingcheng Xiao, Liqiang Lu, Jiaming Xie, Yun Liang
FCNNLib: An Efficient and Flexible Convolution Algorithm Library on FPGAs. DAC (2020)
Yun Liang, Liqiang Lu, Qingcheng Xiao, Shengen Yan
Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (4) (2020)
Liancheng Jia, Yun Liang, Xiuhong Li, Liqiang Lu, Shengen Yan
Enabling Efficient Fast Convolution Algorithms on GPUs via MegaKernels. IEEE Trans. Computers 69 (7) (2020)
Liqiang Lu, Jiaming Xie, Ruirui Huang, Jiansong Zhang, Wei Lin, Yun Liang
An Efficient Hardware Accelerator for Sparse Convolutional Neural Networks on FPGAs. FCCM (2019)
Liqiang Lu, Yun Liang, Ruirui Huang, Wei Lin, Xiaoyuan Cui, Jiansong Zhang
Speedy: An Accelerator for Sparse Convolutional Neural Networks on FPGAs. FPGA (2019)
Liqiang Lu, Yun Liang
SpWA: an efficient sparse winograd convolutional neural networks accelerator on FPGAs. DAC (2018)
Liqiang Lu, Yun Liang, Qingcheng Xiao, Shengen Yan
Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs. FCCM (2017)
Qingcheng Xiao, Yun Liang, Liqiang Lu, Shengen Yan, Yu-Wing Tai
Exploring Heterogeneous Algorithms for Accelerating Deep Convolutional Neural Networks on FPGAs. DAC (2017)