​
Login / Signup
Zizhang Luo
ORCID
Publication Activity (10 Years)
Years Active: 2020-2024
Publications (10 Years): 12
Top Topics
Higher Order
Fpga Hardware
Spatial Constraints
Lego Mindstorms
Top Venues
CoRR
DAC
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
MICRO
</>
Publications
</>
Liqiang Lu
,
Zizhang Luo
,
Size Zheng
,
Jieming Yin
,
Jason Cong
,
Yun Liang
,
Jianwei Yin
Rubick: A Unified Infrastructure for Analyzing, Exploring, and Implementing Spatial Architectures via Dataflow Decomposition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
43 (4) (2024)
Youwei Xiao
,
Zizhang Luo
,
Kexing Zhou
,
Yun Liang
Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis.
FPGA
(2024)
Zizhang Luo
,
Liqiang Lu
,
Size Zheng
,
Jieming Yin
,
Jason Cong
,
Jianwei Yin
,
Yun Liang
Rubick: A Synthesis Framework for Spatial Architectures via Dataflow Decomposition.
DAC
(2023)
Zizhang Luo
,
Liqiang Lu
,
Yicheng Jin
,
Liancheng Jia
,
Yun Liang
Calabash: Accelerating Attention Using a Systolic Array Chain on FPGAs.
FPL
(2023)
Liancheng Jia
,
Zizhang Luo
,
Liqiang Lu
,
Yun Liang
Automatic Generation of Spatial Accelerator for Tensor Algebra.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
42 (6) (2023)
Liancheng Jia
,
Zizhang Luo
,
Liqiang Lu
,
Yun Liang
TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebra.
DAC
(2021)
Liancheng Jia
,
Zizhang Luo
,
Liqiang Lu
,
Yun Liang
TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebra.
CoRR
(2021)
Liqiang Lu
,
Naiqing Guan
,
Yuyue Wang
,
Liancheng Jia
,
Zizhang Luo
,
Jieming Yin
,
Jason Cong
,
Yun Liang
TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation.
ISCA
(2021)
Liqiang Lu
,
Naiqing Guan
,
Yuyue Wang
,
Liancheng Jia
,
Zizhang Luo
,
Jieming Yin
,
Jason Cong
,
Yun Liang
TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation.
CoRR
(2021)
Liqiang Lu
,
Yicheng Jin
,
Hangrui Bi
,
Zizhang Luo
,
Peng Li
,
Tao Wang
,
Yun Liang
Sanger: A Co-Design Framework for Enabling Sparse Attention using Reconfigurable Architecture.
MICRO
(2021)
Liancheng Jia
,
Zizhang Luo
,
Liqiang Lu
,
Yun Liang
Analyzing the Design Space of Spatial Tensor Accelerators on FPGAs.
ISVLSI
(2021)
Zizhang Luo
,
Yuxuan Zhou
,
Bohan Yu
,
Junfeng Hu
Teaching Platform for Network Communication and Protocols Using a Micro: bit Based Wheeled Robot.
SIGCSE
(2020)