Liancheng Jia

Publication Activity (10 Years)

Years Active: 2019-2023
Publications (10 Years): 13

Top Topics

Memory Subsystem

Reconfigurable Architecture

Top Venues

Publications

Size Zheng, Siyuan Chen, Siyuan Gao, Liancheng Jia, Guangyu Sun, Runsheng Wang, Yun Liang
TileFlow: A Framework for Modeling Fusion Dataflow via Tree-based Analysis. MICRO (2023)
Zizhang Luo, Liqiang Lu, Yicheng Jin, Liancheng Jia, Yun Liang
Calabash: Accelerating Attention Using a Systolic Array Chain on FPGAs. FPL (2023)
Liancheng Jia, Zizhang Luo, Liqiang Lu, Yun Liang
Automatic Generation of Spatial Accelerator for Tensor Algebra. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (6) (2023)
Haokun Li, Jing Liu, Liancheng Jia, Yun Liang, Yaowei Wang, Mingkui Tan
Downscaling and Overflow-aware Model Compression for Efficient Vision Processors. ICDCS Workshops (2022)
Liancheng Jia, Yuyue Wang, Jingwen Leng, Yun Liang
EMS: efficient memory subsystem synthesis for spatial accelerators. DAC (2022)
Liancheng Jia, Zizhang Luo, Liqiang Lu, Yun Liang
TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebra. DAC (2021)
Liancheng Jia, Zizhang Luo, Liqiang Lu, Yun Liang
TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebra. CoRR (2021)
Liqiang Lu, Naiqing Guan, Yuyue Wang, Liancheng Jia, Zizhang Luo, Jieming Yin, Jason Cong, Yun Liang
TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation. ISCA (2021)
Liqiang Lu, Naiqing Guan, Yuyue Wang, Liancheng Jia, Zizhang Luo, Jieming Yin, Jason Cong, Yun Liang
TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation. CoRR (2021)
Liancheng Jia, Zizhang Luo, Liqiang Lu, Yun Liang
Analyzing the Design Space of Spatial Tensor Accelerators on FPGAs. ISVLSI (2021)
Liancheng Jia, Liqiang Lu, Xuechao Wei, Yun Liang
Generating Systolic Array Accelerators With Reusable Blocks. IEEE Micro 40 (4) (2020)
Liancheng Jia, Yun Liang, Xiuhong Li, Liqiang Lu, Shengen Yan
Enabling Efficient Fast Convolution Algorithms on GPUs via MegaKernels. IEEE Trans. Computers 69 (7) (2020)
Xiuhong Li, Yun Liang, Shengen Yan, Liancheng Jia, Yinghan Li
A coordinated tiling and batching framework for efficient GEMM on GPUs. PPoPP (2019)