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Generating Systolic Array Accelerators With Reusable Blocks.

Liancheng JiaLiqiang LuXuechao WeiYun Liang
Published in: IEEE Micro (2020)
Keyphrases
  • systolic array
  • reconfigurable architecture
  • data flow
  • parallel architecture
  • computing systems
  • block size
  • computing platform
  • single chip
  • image segmentation
  • multi view
  • fractal image coding