Larysa Titarenko

Publication Activity (10 Years)

Years Active: 2007-2024
Publications (10 Years): 26

Top Topics

Functional Decomposition

Embedded Systems

Top Venues

Int. J. Appl. Math. Comput. Sci.

J. Circuits Syst. Comput.

Publications

Larysa Titarenko, Vyacheslav Kharchenko, Vadym Puidenko, Artem Perepelitsyn, Alexander Barkalov
Hardware-Based Implementation of Algorithms for Data Replacement in Cache Memory of Processor Cores. Comput. 13 (7) (2024)
Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Malgorzata Mazurkiewicz
Hardware Reduction for FSMs With Extended State Codes. IEEE Access 12 (2024)
Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
Reducing the number of LUTs for Mealy FSMs with state transformation. Int. J. Appl. Math. Comput. Sci. 34 (1) (2024)
Alexander A. Barkalov, Larysa Titarenko, Kamil Mielcarek
Reducing LUT Count for Mealy FSMs With Transformation of States. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (5) (2022)
Alexander Barkalov, Larysa Titarenko, Malgorzata Mazurkiewicz
Improving the LUT Count for Mealy FSMS with Transformation of Output Collections. Int. J. Appl. Math. Comput. Sci. 32 (3) (2022)
Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski, Kamil Mielcarek
Improving Characteristics of FSMs With Mixed Codes of Outputs. IEEE Access 10 (2022)
Kazimierz Krzywicki, Grzegorz Andrzejewski, Wojciech Zajac, Tomasz Królikowski, Alexander Barkalov, Larysa Titarenko
IPNES - Interpreted Petri Net for Embedded Systems. KES (2021)
Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
Improving Characteristics of LUT-Based Moore FSMs. IEEE Access 8 (2020)
Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
Improving characteristics of LUT-based Mealy FSMs. Int. J. Appl. Math. Comput. Sci. 30 (4) (2020)
Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
Designing FPGA-Based Mealy FSMs with Two Levels of Logic. MOCAST (2019)
Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Kazimierz Krzywicki, Wojciech Zajac
Decreasing Number of LUTs for Moore FSMs. MIXDES (2019)
Alexander Barkalov, Larysa Titarenko, Malgorzata Mazurkiewicz, Kamil Mielcarek
Encoding of Microoperations in FPGA-Based Moore FSMs. MOCAST (2019)
Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
Mixed Encoding of Collections of Output Variables for LUT-Based Mealy FSMs. J. Circuits Syst. Comput. 28 (8) (2019)
Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski, Kamil Mielcarek
Design of FPGA-Based Mealy FSMs with Counters. MOCAST (2019)
Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
Twofold state assignment for FPGA-based mealy FSMs. MOCAST (2018)
Alexander Barkalov, Larysa Titarenko, Malgorzata Mazurkiewicz, Kamil Mielcarek
Encoding of Terms in LUT-based Mealy FSMs. MIXDES (2018)
Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Slawomir Chmielewski
Design of FPGA-based Mealy FSMs with Counters. MIXDES (2018)
Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
Hardware Reduction for Lut-Based Mealy FSMs. Int. J. Appl. Math. Comput. Sci. 28 (3) (2018)
Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
Twofold State Assignment for LUT-based Mealy FSMs. MIXDES (2018)
Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
Design of CPLD-based mealy FSMs with counters. MOCAST (2018)
Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski
Code sharing in CPLD-based Moore FSMs. MOCAST (2017)
Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski
Designing HFPGA-based FSMs with counters. MIXDES (2017)
Kazimierz Krzywicki, Alexander Barkalov, Grzegorz Andrzejewski, Larysa Titarenko, Malgorzata Kolopienczyk
CloudBus protocol hardware multi-converter gateway for distributed embedded systems. MIXDES (2017)
Kamil Mielcarek, Alexander Barkalov, Larysa Titarenko
Designing HFPGA-based Mealy FSMs with transformation of output functions. MIXDES (2017)
Kamil Mielcarek, Alexander Barkalov, Larysa Titarenko
Designing Moore FSM with extended class codes. MOCAST (2017)
Malgorzata Kolopienczyk, Larysa Titarenko, Alexander Barkalov
Design of EMB-Based Moore FSMs. J. Circuits Syst. Comput. 26 (7) (2017)
Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
Hardware Reduction in CPLD-Based Moore FSM. J. Circuits Syst. Comput. 23 (6) (2014)
Larysa Titarenko, Olena Hebda, Alexander Barkalov
Design of Moore finite state machine with coding space stretching. HSI (2014)
Malgorzata Kolopienczyk, Alexander Barkalov, Larysa Titarenko
Hardware reduction for RAM-based Moore FSMs. HSI (2014)
Alexander Barkalov, Larysa Titarenko, Lukasz Smolinski
Hardware reduction for compositional microprogram control unit dedicated for CPLD systems. EWDTS (2013)
Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski
Design of FPGA-Based Moore FMSs with Counters. PDeS (2013)
Alexander Barkalov, Larysa Titarenko, Roman Babakov
Compositional Microprogram Control Unit with Operational Automaton of Transitions. PDeS (2013)
Alexander Barkalov, Larysa Titarenko, Malgorzata Kolopienczyk
EMB - Based Design of Mealy FSM. PDeS (2013)
Larysa Titarenko, Olena Hebda
Matrix implementation of Moore FSM with nonstandard presentation of state codes. EWDTS (2013)
Alexander Barkalov, Slawomir Chmielewski, Larysa Titarenko
Synthesis of Moore Finite State Machines Based on Pseudoequivalent States. PDeS (2013)
Larysa Titarenko, Olena Hebda, Alexander Barkalov
Synthesis of PLA-Based Moore FSM with Unconventional Presentation of State Codes. PDeS (2013)
Alexander Barkalov, Larysa Titarenko, Raisa Malcheva, Kyryll Soldatov
Hardware Reduction in FPGA-Based Moore FSM. J. Circuits Syst. Comput. 22 (3) (2013)
Alexander Barkalov, Roman Babakov, Larysa Titarenko
Compositional microprogram control unit with operational automaton of transitions. EWDTS (2013)
Larysa Titarenko, Olena Hebda, Alexander Barkalov
Design of moore finite state machine with extended state codes. ITI (2013)
Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
Synthesis of control unit with refined state encoding for CPLD devices. EWDTS (2011)
Remigiusz Wisniewski, Alexander Barkalov, Larysa Titarenko, Wolfgang A. Halang
Design of microprogrammed controllers to be implemented in FPGAs. Int. J. Appl. Math. Comput. Sci. 21 (2) (2011)
Alexander Barkalov, Larysa Titarenko, Lukasz Smolinski
Optimization of microprogram control unit with code sharing. EWDTS (2011)
Alexander Barkalov, Larysa Titarenko, Olena Hebda
Hardware reduction for matrix circuit of control Moore automaton. EWDTS (2011)
Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
Hardware reduction for FSM - Based control units using PAL technology. EWDTS (2010)
Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
Reduction in the number of PAL macrocells for Moore FSM implemented with CPLD. EWDTS (2010)
Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski
Reduction in the number of LUT elements for control units with code sharing. Int. J. Appl. Math. Comput. Sci. 20 (4) (2010)
Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski
Microprogram control unit with code sharing and extended microinstruction format. EWDTS (2010)
Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSM. Int. J. Appl. Math. Comput. Sci. 17 (4) (2007)