Kamil Mielcarek

Publication Activity (10 Years)

Years Active: 2017-2024
Publications (10 Years): 17

Top Topics

Encoding Schemes

Hardware Software Partitioning

Inverse Halftoning

Top Venues

Int. J. Appl. Math. Comput. Sci.

Publications

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Malgorzata Mazurkiewicz
Hardware Reduction for FSMs With Extended State Codes. IEEE Access 12 (2024)
Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
Reducing the number of LUTs for Mealy FSMs with state transformation. Int. J. Appl. Math. Comput. Sci. 34 (1) (2024)
Alexander A. Barkalov, Larysa Titarenko, Kamil Mielcarek
Reducing LUT Count for Mealy FSMs With Transformation of States. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (5) (2022)
Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski, Kamil Mielcarek
Improving Characteristics of FSMs With Mixed Codes of Outputs. IEEE Access 10 (2022)
Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
Improving characteristics of LUT-based Mealy FSMs. Int. J. Appl. Math. Comput. Sci. 30 (4) (2020)
Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
Designing FPGA-Based Mealy FSMs with Two Levels of Logic. MOCAST (2019)
Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Kazimierz Krzywicki, Wojciech Zajac
Decreasing Number of LUTs for Moore FSMs. MIXDES (2019)
Alexander Barkalov, Larysa Titarenko, Malgorzata Mazurkiewicz, Kamil Mielcarek
Encoding of Microoperations in FPGA-Based Moore FSMs. MOCAST (2019)
Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski, Kamil Mielcarek
Design of FPGA-Based Mealy FSMs with Counters. MOCAST (2019)
Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
Twofold state assignment for FPGA-based mealy FSMs. MOCAST (2018)
Alexander Barkalov, Larysa Titarenko, Malgorzata Mazurkiewicz, Kamil Mielcarek
Encoding of Terms in LUT-based Mealy FSMs. MIXDES (2018)
Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Slawomir Chmielewski
Design of FPGA-based Mealy FSMs with Counters. MIXDES (2018)
Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
Hardware Reduction for Lut-Based Mealy FSMs. Int. J. Appl. Math. Comput. Sci. 28 (3) (2018)
Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
Twofold State Assignment for LUT-based Mealy FSMs. MIXDES (2018)
Kamil Mielcarek, Alexander Barkalov, Larysa Titarenko
Designing HFPGA-based Mealy FSMs with transformation of output functions. MIXDES (2017)
Kamil Mielcarek, Alexander Barkalov, Larysa Titarenko
Designing Moore FSM with extended class codes. MOCAST (2017)
Kamil Mielcarek, Alexander Barkalov, Larisa Titarenko
Designing Moore FSM with Transformation of State Codes. CISIM (2017)