Slawomir Chmielewski

Publication Activity (10 Years)

Years Active: 2007-2022
Publications (10 Years): 6

Top Topics

Encoding Scheme

Finite State Machines

Programmable Logic

Top Venues

J. Circuits Syst. Comput.

Publications

Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski, Kamil Mielcarek
Improving Characteristics of FSMs With Mixed Codes of Outputs. IEEE Access 10 (2022)
Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
Improving Characteristics of LUT-Based Moore FSMs. IEEE Access 8 (2020)
Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
Mixed Encoding of Collections of Output Variables for LUT-Based Mealy FSMs. J. Circuits Syst. Comput. 28 (8) (2019)
Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski, Kamil Mielcarek
Design of FPGA-Based Mealy FSMs with Counters. MOCAST (2019)
Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Slawomir Chmielewski
Design of FPGA-based Mealy FSMs with Counters. MIXDES (2018)
Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
Design of CPLD-based mealy FSMs with counters. MOCAST (2018)
Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
Hardware Reduction in CPLD-Based Moore FSM. J. Circuits Syst. Comput. 23 (6) (2014)
Alexander Barkalov, Slawomir Chmielewski, Larysa Titarenko
Synthesis of Moore Finite State Machines Based on Pseudoequivalent States. PDeS (2013)
Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
Synthesis of control unit with refined state encoding for CPLD devices. EWDTS (2011)
Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
Hardware reduction for FSM - Based control units using PAL technology. EWDTS (2010)
Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
Reduction in the number of PAL macrocells for Moore FSM implemented with CPLD. EWDTS (2010)
Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski
Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSM. Int. J. Appl. Math. Comput. Sci. 17 (4) (2007)