Hardware Reduction in CPLD-Based Moore FSM.
Alexander BarkalovLarysa TitarenkoSlawomir ChmielewskiPublished in: J. Circuits Syst. Comput. (2014)
Keyphrases
- programmable logic
- low cost
- hardware and software
- real time
- hardware architecture
- reduction method
- computing power
- finite state machines
- hardware description language
- digital signal processor
- hardware implementation
- data acquisition
- computer systems
- image processing
- input output
- field programmable gate array
- data processing
- evolutionary algorithm
- software implementation
- vlsi implementation
- control program
- data structure
- standard pc
- information retrieval