Josep Llosa

Publication Activity (10 Years)

Years Active: 1994-2022
Publications (10 Years): 2

Top Topics

Coronary Artery

Recent Progress

Top Venues

Comput. Phys. Commun.

Publications

Apan Qasem, Hartwig Anzt, Eduard Ayguadé, Katharine Cahill, Ramon Canal, Jany Chan, Eric Fosler-Lussier, Fritz Göbel, Arpan Jain, Marcel Koch, Mateusz Kuzak, Josep Llosa, Raghu Machiraju, Xavier Martorell, Pratik Nayak, Shameema Oottikkal, Marcin Ostasz, Dhabaleswar K. Panda, Dirk Pleiter, Rajiv Ramnath, Maria-Ribera Sancho, Alessio Sclocco, Aamir Shafi, Hanno Spreeuw, Hari Subramoni, Karen Tomko
Lightning Talks of EduHPC 2022. EduHPC@SC (2022)
Francesc Salvat, Josep Llosa, Antonio M. Lallena, Julio Almansa
ECCPA: Calculation of classical and quantum cross sections for elastic collisions of charged particles with atoms. Comput. Phys. Commun. 277 (2022)
Manoj Gupta, Fermín Sánchez, Josep Llosa
A low cost split-issue technique to improve performance of SMT clustered VLIW processors. IPDPS (2010)
Manoj Gupta, Fermín Sánchez, Josep Llosa
CSMT: Simultaneous Multithreading for Clustered VLIW Processors. IEEE Trans. Computers 59 (3) (2010)
Manoj Gupta, Fermín Sánchez, Josep Llosa
Thread Merging Schemes for Multithreaded Clustered VLIW Processors. ICPP (2009)
Manoj Gupta, Fermín Sánchez, Josep Llosa
Hybrid multithreading for VLIW processors. CASES (2009)
Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
Power-efficient VLIW design using clustering and widening. Int. J. Embed. Syst. 3 (3) (2008)
Manoj Gupta, Fermín Sánchez, Josep Llosa
Cluster-level simultaneous multithreading for VLIW processors. ICCD (2007)
Kolin Paul, Joel Porquet, Josep Llosa
Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration. DSD (2007)
Manoj Gupta, Fermín Sánchez, Josep Llosa
Merge Logic for Clustered Multithreaded VLIW Processors. DSD (2007)
Xavier Vera, Jaume Abella, Josep Llosa, Antonio González
An accurate cost model for guiding data locality transformations. ACM Trans. Program. Lang. Syst. 27 (5) (2005)
Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero
Out-of-Order Commit Processors. HPCA (2004)
Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units. SAMOS (2004)
Xavier Vera, Nerina Bermudo, Josep Llosa, Antonio González
A fast and accurate framework to analyze and optimize cache memory behavior. ACM Trans. Program. Lang. Syst. 26 (2) (2004)
Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures. Int. J. Parallel Program. 32 (6) (2004)
Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero
A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors. SIGARCH Comput. Archit. News 32 (3) (2004)
Adrián Cristal, Josep Llosa, Mateo Valero, Daniel Ortega
Future ILP processors. Int. J. High Perform. Comput. Netw. 2 (1) (2004)
Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
Register Constrained Modulo Scheduling. IEEE Trans. Parallel Distributed Syst. 15 (5) (2004)
Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
High-performance and low-power VLIW cores for numerical computations. Int. J. High Perform. Comput. Netw. 1 (4) (2004)
Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero
A Case for Resource-conscious Out-of-order Processors. IEEE Comput. Archit. Lett. 2 (2003)
Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes. ISHPC (2003)
Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero
Kilo-instruction Processors. ISHPC (2003)
Xavier Vera, Jaume Abella, Antonio González, Josep Llosa
Optimizing Program Locality Through CMEs and GAs. IEEE PACT (2003)
Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
Hierarchical Clustered Register File Organization for VLIW Processors. IPDPS (2003)
Xavier Vera, Josep Llosa, Antonio González
Near-Optimal Padding for Removing Conflict Misses. LCPC (2002)
Josep M. Codina, Josep Llosa, Antonio González
A comparative study of modulo scheduling techniques. ICS (2002)
Jaume Abella, Antonio González, Josep Llosa, Xavier Vera
Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms. ICPP Workshops (2002)
Josep Llosa, Stefan M. Freudenberger
Reduced code size modulo scheduling in the absence of hardware support. MICRO (2002)
Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
Modulo scheduling with integrated register spilling for clustered VLIW architectures. MICRO (2001)
David López, Josep Llosa, Mateo Valero, Eduard Ayguadé
Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures. IEEE Trans. Computers 50 (10) (2001)
Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
: Modulo Scheduling with Integrated Register Spilling. LCPC (2001)
Josep Llosa, Eduard Ayguadé, Antonio González, Mateo Valero, Jason Eckhardt
Lifetime-Sensitive Modulo Scheduling in a Production Environment. IEEE Trans. Computers 50 (3) (2001)
Xavier Vera, Josep Llosa, Antonio González, Nerina Bermudo
A Fast and Accurate Approach to Analyze Cache Memory Behavior (Research Note). Euro-Par (2000)
Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
Two-level hierarchical register file organization for VLIW processors. MICRO (2000)
Nerina Bermudo, Xavier Vera, Antonio González, Josep Llosa
Optimizing cache miss equations polyhedra. SIGARCH Comput. Archit. News 28 (1) (2000)
Nerina Bermudo, Xavier Vera, Antonio González, Josep Llosa
An efficient solver for Cache Miss Equations. ISPASS (2000)
Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
Improved spill code generation for software pipelined loops. PLDI (2000)
Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham
Distributed Modulo Scheduling. HPCA (1999)
David López, Josep Llosa, Eduard Ayguadé, Mateo Valero
Impact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures. ICPP (1999)
Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González
Modulo Scheduling with Reduced Register Pressure. IEEE Trans. Computers 47 (6) (1998)
Josep Llosa, Eduard Ayguadé, Mateo Valero
Quantitative Evaluation of Register Pressure on Software Pipelined Loops. Int. J. Parallel Program. 26 (2) (1998)
Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham
Partitioned Schedules for Clustered VLIW Architectures. IPPS/SPDP (1998)
David López, Josep Llosa, Mateo Valero, Eduard Ayguadé
Resource Widening Versus Replication: Limits and Performance-cost Trade-off. International Conference on Supercomputing (1998)
David López, Josep Llosa, Mateo Valero, Eduard Ayguadé
Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures. MICRO (1998)
David López, Mateo Valero, Josep Llosa, Eduard Ayguadé
Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs. International Conference on Supercomputing (1997)
Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham
Allocating Lifetimes to Queues in Software Pipelined Architectures. Euro-Par (1997)
Josep Llosa, Antonio González, Eduard Ayguadé, Mateo Valero
Swing module scheduling: a lifetime-sensitive approach. IEEE PACT (1996)
Josep Llosa, Mateo Valero, Eduard Ayguadé
Heuristics for Register-Constrained Software Pipelining. MICRO (1996)
Josep Llosa, Mateo Valero, Eduard Ayguadé
Non-Consistent Dual Register Files to Reduce Register Pressure. HPCA (1995)
Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González
Hypernode reduction modulo scheduling. MICRO (1995)
Josep Llosa, Mateo Valero, José A. B. Fortes, Eduard Ayguadé
Using Sacks to Organize Registers in VLIW Machines. CONPAR (1994)