Josep M. Codina

Publication Activity (10 Years)

Years Active: 2001-2015
Publications (10 Years): 0

Top Topics

Runtime Environment

Top Venues

IEEE Comput. Archit. Lett.

Publications

Enric Gibert, Raúl Martínez, Carlos Madriles, Josep M. Codina
Profiling Support for Runtime Managed Code: Next Generation Performance Monitoring Units. IEEE Comput. Archit. Lett. 14 (1) (2015)
Abhishek Deb, Josep M. Codina, Antonio González
A HW/SW Co-designed Programmable Functional Unit. IEEE Comput. Archit. Lett. 11 (1) (2012)
Abhishek Deb, Josep M. Codina, Antonio González
A Co-designed HW/SW Approach to General Purpose Program Acceleration Using a Programmable Functional Unit. Interaction between Compilers and Computer Architectures (2011)
Abhishek Deb, Josep M. Codina, Antonio González
A Power-Efficient Co-designed Out-of-Order Processor. SBAC-PAD (2011)
Abhishek Deb, Josep M. Codina, Antonio González
SoftHV: a HW/SW co-designed processor with horizontal and vertical fusion. Conf. Computing Frontiers (2011)
Carlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González
Boosting single-thread performance in multi-core systems through fine-grain multi-threading. ISCA (2009)
Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González, David R. Kaeli
AGAMOS: A Graph-Based Approach to Modulo Scheduling for Clustered Microarchitectures. IEEE Trans. Computers 58 (6) (2009)
Carlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González
Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading. PACT (2009)
Qiong Cai, Josep M. Codina, José González, Antonio González
A software-hardware hybrid steering mechanism for clustered microarchitectures. IPDPS (2008)
Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli
Heterogeneous Clustered VLIW Microarchitectures. CGO (2007)
Josep M. Codina, F. Jesús Sánchez, Antonio González
Virtual Cluster Scheduling Through the Scheduling Graph. CGO (2007)
Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli
Demystifying on-the-fly spill code. PLDI (2005)
Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli
Removing communications in clustered microarchitectures through instruction replication. ACM Trans. Archit. Code Optim. 1 (2) (2004)
Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli
Instruction Replication for Clustered Microarchitectures. MICRO (2003)
Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González, David R. Kaeli
Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning. IEEE PACT (2002)
Josep M. Codina, Josep Llosa, Antonio González
A comparative study of modulo scheduling techniques. ICS (2002)
Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González
Graph-partitioning based instruction scheduling for clustered processors. MICRO (2001)
Josep M. Codina, F. Jesús Sánchez, Antonio González
A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors. IEEE PACT (2001)