Javier Zalamea

Publication Activity (10 Years)

Years Active: 2000-2008
Publications (10 Years): 0

Publications

Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
Power-efficient VLIW design using clustering and widening. Int. J. Embed. Syst. 3 (3) (2008)
Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units. SAMOS (2004)
Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures. Int. J. Parallel Program. 32 (6) (2004)
Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
Register Constrained Modulo Scheduling. IEEE Trans. Parallel Distributed Syst. 15 (5) (2004)
Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
High-performance and low-power VLIW cores for numerical computations. Int. J. High Perform. Comput. Netw. 1 (4) (2004)
Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes. ISHPC (2003)
Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
Hierarchical Clustered Register File Organization for VLIW Processors. IPDPS (2003)
Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
Modulo scheduling with integrated register spilling for clustered VLIW architectures. MICRO (2001)
Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
: Modulo Scheduling with Integrated Register Spilling. LCPC (2001)
Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
Two-level hierarchical register file organization for VLIW processors. MICRO (2000)
Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
Improved spill code generation for software pipelined loops. PLDI (2000)