Jing Tian

Publication Activity (10 Years)

Years Active: 2018-2024
Publications (10 Years): 43

Top Topics

Decoding Algorithm

Low Density Parity Check

Hardware Implementation

Top Venues

IACR Cryptol. ePrint Arch.

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Jing Tian, Bo Wu, Lang Feng, Haochen Zhang, Zhongfeng Wang
A Fast and Efficient SIKE Co-Design: Coarse-Grained Reconfigurable Accelerators with Custom RISC-V Microcontroller on FPGA. IACR Cryptol. ePrint Arch. 2024 (2024)
Xinyuan Qiao, Suwen Song, Jing Tian, Zhongfeng Wang
Efficient Decryption Architecture for Classic McEliece. ISQED (2023)
Yifeng Song, Xiao Hu, Jing Tian, Zhongfeng Wang
A High-Speed FPGA-Based Hardware Implementation for Leighton-Micali Signature. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (1) (2023)
Minghao Li, Jing Tian, Xiao Hu, Zhongfeng Wang
Reconfigurable and High-Efficiency Polynomial Multiplication Accelerator for CRYSTALS-Kyber. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (8) (2023)
Yueqin Dai, Yifeng Song, Jing Tian, Zhongfeng Wang
High-Throughput Hardware Implementation for Haraka in SPHINCS+. ISQED (2023)
Lun Ou, Danyang Zhu, Jing Tian, Zhongfeng Wang
Fast Hardware Implementation for Extended GCD of Large Numbers in Redundant Representation. IEEE Trans. Circuits Syst. II Express Briefs 70 (8) (2023)
Huiyang Xiong, Bohang Xiong, Wenhao Wang, Jing Tian, Hao Zhu, Zhongfeng Wang
Efficient FPGA-Based Accelerator of the L-BFGS Algorithm for IoT Applications. ISCAS (2023)
Xiao Hu, Jing Tian, Minghao Li, Zhongfeng Wang
AC-PM: An Area-Efficient and Configurable Polynomial Multiplier for Lattice Based Cryptography. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (2) (2023)
Danyang Zhu, Rongrong Zhang, Lun Ou, Jing Tian, Zhongfeng Wang
Low-Latency Design and Implementation of the Squaring in Class Groups for Verifiable Delay Function Using Redundant Representation. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2023 (1) (2023)
Chen Li, Suwen Song, Jing Tian, Zhongfeng Wang, Çetin Kaya Koç
An Efficient Hardware Design for Fast Implementation of HQC. SOCC (2023)
Danyang Zhu, Jing Tian, Minghao Li, Zhongfeng Wang
Low-latency Hardware Architecture for VDF Evaluation in Class Groups. IEEE Trans. Computers 72 (6) (2023)
Bohang Xiong, Jing Tian, Zhongfeng Wang
A High-Speed Codec Architecture for Lagrange Coded Computing. ISCAS (2022)
Xiao Hu, Minghao Li, Jing Tian, Zhongfeng Wang
Efficient Homomorphic Convolution Designs on FPGA for Secure Inference. IEEE Trans. Very Large Scale Integr. Syst. 30 (11) (2022)
Lei Yang, Jing Tian, Bo Wu, Zhongfeng Wang, Hao Ren
An RS-BCH Concatenated FEC Code for Beyond 400 Gb/s Networking. ISVLSI (2022)
Jing Tian, Piaoyang Wang, Zhe Liu, Jun Lin, Zhongfeng Wang, Johann Großschädl
Efficient Software Implementation of the SIKE Protocol Using a New Data Representation. IEEE Trans. Computers 71 (3) (2022)
Minghao Li, Jing Tian, Xiao Hu, Yuan Cao, Zhongfeng Wang
High-Speed and Low-Complexity Modular Reduction Design for CRYSTALS-Kyber. APCCAS (2022)
Samira Carolina Oliva Madrigal, Gökay Saldamli, Chen Li, Yue Geng, Jing Tian, Zhongfeng Wang, Çetin Kaya Koç
Reduction-Free Multiplication for Finite Fields and Polynomial Rings. WAIFI (2022)
Danyang Zhu, Jing Tian, Minghao Li, Zhongfeng Wang
Low-latency Hardware Architecture for VDF Evaluation in Class Groups. IACR Cryptol. ePrint Arch. 2022 (2022)
Jing Tian, Bo Wu, Zhongfeng Wang
High-Speed FPGA Implementation of SIKE Based on an Ultra-Low-Latency Modular Multiplier. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (9) (2021)
Xiao Hu, Minghao Li, Jing Tian, Zhongfeng Wang
DARM: A Low-Complexity and Fast Modular Multiplier for Lattice-Based Cryptography. ASAP (2021)
Danyang Zhu, Jing Tian, Zhongfeng Wang
Low-Latency Architecture for the Parallel Extended GCD Algorithm of Large Numbers. ISCAS (2021)
Yifeng Song, Xiao Hu, Wenhao Wang, Jing Tian, Zhongfeng Wang
High-Speed and Scalable FPGA Implementation of the Key Generation for the Leighton-Micali Signature Protocol. ISCAS (2021)
Jing Tian, Jun Lin, Zhongfeng Wang
Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography. IEEE Trans. Very Large Scale Integr. Syst. 29 (2) (2021)
Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang
An Improved Reliability-Based Decoding Algorithm for NB-LDPC Codes. IEEE Commun. Lett. 25 (4) (2021)
Yifeng Song, Danyang Zhu, Jing Tian, Zhongfeng Wang
A High-Speed Architecture for the Reduction in VDF Based on a Class Group. IACR Cryptol. ePrint Arch. 2021 (2021)
Jing Tian, Jun Lin, Zhongfeng Wang
Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography. IACR Cryptol. ePrint Arch. 2020 (2020)
Jing Tian, Bo Wu, Zhongfeng Wang
High-Speed FPGA Implementation of the SIKE Based on An Ultra-Low-Latency Modular Multiplier. IACR Cryptol. ePrint Arch. 2020 (2020)
Jing Tian, Suwen Song, Jun Lin, Zhongfeng Wang
Optimized Trellis-Based Min-Max Decoder for NB-LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs (1) (2020)
Bo Wu, Jing Tian, Xiao Hu, Zhongfeng Wang
A Novel Modular Multiplier for Isogeny-Based Post-Quantum Cryptography. ISVLSI (2020)
Xiao Hu, Jing Tian, Zhongfeng Wang
Fast Permutation Architecture on Encrypted Data for Secure Neural Network Inference. APCCAS (2020)
Suwen Song, Hangxuan Cui, Jing Tian, Jun Lin, Zhongfeng Wang
A Novel Iterative Reliability-Based Majority-Logic Decoder for NB-LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs (8) (2020)
Yifeng Song, Danyang Zhu, Jing Tian, Zhongfeng Wang
A High-Speed Architecture for the Reduction in VDF Based on a Class Group. SoCC (2020)
Danyang Zhu, Yifeng Song, Jing Tian, Zhongfeng Wang, Haobo Yu
An Efficient Accelerator of the Squaring for the Verifiable Delay Function Over a Class Group. APCCAS (2020)
Jing Tian, Piaoyang Wang, Zhe Liu, Jun Lin, Zhongfeng Wang, Johann Großschädl
Faster Software Implementation of the SIKE Protocol Based on A New Data Representation. IACR Cryptol. ePrint Arch. 2020 (2020)
Jing Tian, Suwen Song, Jun Lin, Zhongfeng Wang
Efficient T-EMS Based Decoding Algorithms for High-Order LDPC Codes. IEEE Access 7 (2019)
Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang
A Novel Low-Complexity Joint Coding and Decoding Algorithm for NB-LDPC Codes. ISCAS (2019)
Jing Tian, Jun Lin, Zhongfeng Wang
Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography. SiPS (2019)
Wenjie Li, Jing Tian, Jun Lin, Zhongfeng Wang
Modified GII-BCH Codes for Low-Complexity and Low-Latency Encoders. IEEE Commun. Lett. 23 (5) (2019)
Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang
Redundancy-Aided Iterative Reliability-Based Majority-Logic Decoding for NB-LDPC Codes. ASICON (2019)
Jing Tian, Zhe Liu, Jun Lin, Zhongfeng Wang, Binjing Li
High-Speed Modular Multipliers for Isogeny-Based Post-Quantum Cryptography. IACR Cryptol. ePrint Arch. 2019 (2019)
Jing Tian, Jun Lin, Zhongfeng Wang
A 21.66 Gbps Nonbinary LDPC Decoder for High-Speed Communications. IEEE Trans. Circuits Syst. II Express Briefs (2) (2018)
Jing Tian, Jun Lin, Zhongfeng Wang
Analysis of the Dual-Threshold-Based Shrinking Scheme for Efficient NB-LDPC Decoding. APCCAS (2018)
Jing Tian, Jun Lin, Zhongfeng Wang
An Efficient NB-LDPC Decoding Algorithm for Next-Generation Memories. ISCAS (2018)