Jean-Luc Dekeyser

Publication Activity (10 Years)

Years Active: 1990-2019
Publications (10 Years): 7

Top Venues

Microprocess. Microsystems

FPGA

ReCoSoC

Int. J. Reconfigurable Comput.

Publications

Hana Krichene, Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid
SCAC: Weakly-coupled execution model for massively parallel systems. Microprocess. Microsystems 64 (2019)
Karim M. A. Ali, Rabie Ben Atitallah, Abdessamad Ait El Cadi, Nizar Fakhfakh, Jean-Luc Dekeyser
ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures. Int. J. Reconfigurable Comput. 2019 (2019)
Rabie Ben Atitallah, Venkatasubramanian Viswanathan, Nicolas Bélanger, Jean-Luc Dekeyser
FPGA-Centric Design Process for Avionic Simulation and Test. IEEE Trans. Aerosp. Electron. Syst. 54 (3) (2018)
Gilberto Ochoa-Ruiz, Pamela Wattebled, Maamar Touiza, Florent de Lamotte, El-Bay Bourennane, Samy Meftali, Jean-Luc Dekeyser, Jean-Philippe Diguet
A modeling front-end for seamless design and generation of context-aware Dynamically Reconfigurable Systems-on-Chip. J. Parallel Distributed Comput. 112 (2018)
Karim M. A. Ali, Rabie Ben Atitallah, Nizar Fakhfakh, Jean-Luc Dekeyser
Exploring HLS Optimizations for Efficient Stereo Matching Hardware Implementation. ARC (2017)
Wissem Chouchene, Rabie Ben Atitallah, Jean-Luc Dekeyser
AFFORDe: Automatic Allocation and Floorplanning for SPMD Architecture. MCSoC (2016)
Hana Krichene, Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid
SCAC-Net: Reconfigurable Interconnection Network in SCAC Massively Parallel SoC. PDP (2016)
Jean-Luc Dekeyser, A. Shadi Aljendi
Adopting new learning strategies for computer architecture in higher education: case study: building the S3 microprocessor in 24 hours. WCAE (2015)
Vincent Aranega, Jean-Marie Mottu, Anne Etien, Thomas Degueule, Benoit Baudry, Jean-Luc Dekeyser
Towards an automation of the mutation analysis dedicated to model transformation. Softw. Test. Verification Reliab. 25 (5-7) (2015)
Karim M. A. Ali, Rabie Ben Atitallah, Nizar Fakhfakh, Jean-Luc Dekeyser
Using hardware parallelism for reducing power consumption in video streaming applications. ReCoSoC (2015)
Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser, Benjamin Nakache, Maurice Nakache
A Parallel And Scalable Multi-FPGA based Architecture for High Performance Applications (Abstract Only). FPGA (2015)
Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser
Massively Parallel Dynamically Reconfigurable Multi-FPGA Computing System. FCCM (2015)
Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid
FPGA-based many-core System-on-Chip design. Microprocess. Microsystems 39 (4-5) (2015)
Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Jean-Luc Dekeyser
Adaptivity in high-performance embedded systems: a reactive control model for reliable and flexible design. Knowl. Eng. Rev. 29 (4) (2014)
Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser, Benjamin Nakache, Maurice Nakache
Redefining the role of FPGAs in the next generation avionic systems (abstract only). FPGA (2014)
Mokhtar Bouain, Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser
Communication-centric design for FMC based I/O system. ReCoSoC (2014)
Karim M. A. Ali, Rabie Ben Atitallah, Saïd Hanafi, Jean-Luc Dekeyser
A generic pixel distribution architecture for parallel video processing. ReConFig (2014)
Chiraz Trabelsi, Samy Meftali, Rabie Ben Atitallah, Jean-Luc Dekeyser
Model-driven design flow for distributed control in reconfigurable FPGA systems. DASIP (2014)
Antonio Wendell De Oliveira Rodrigues, Frédéric Guyomarc'h, Jean-Luc Dekeyser
An MDE Approach for Automatic Code Generation from UML/MARTE to OpenCL. Comput. Sci. Eng. 15 (1) (2013)
Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser
Decentralized control for dynamically reconfigurable FPGA systems. Microprocess. Microsystems 37 (8-A) (2013)
Hana Krichene, Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser
Master-Slave Control Structure for Massively Parallel System on Chip. DSD (2013)
Majdi Elhaji, Abdelkrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, Rached Tourki
A low-power oriented architecture for H.264 variable block size motion estimation based on a resource sharing scheme. Integr. 46 (4) (2013)
Majdi Elhaji, Pierre Boulet, Abdelkrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, Rached Tourki
System level modeling methodology of NoC design from UML-MARTE to VHDL. Des. Autom. Embed. Syst. 16 (4) (2012)
Gilberto Ochoa-Ruiz, Ouassila Labbani, El-Bay Bourennane, Sana Cherif, Samy Meftali, Jean-Luc Dekeyser
Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT. RSP (2012)
Adolf Samir Abdallah, Abdoulaye Gamatié, Rabie Ben Atitallah, Jean-Luc Dekeyser
Abstract Clock-Based Design of a JPEG Encoder. IEEE Embed. Syst. Lett. 4 (2) (2012)
Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser
Semi-distributed Control for FPGA-based Reconfigurable Systems. DSD (2012)
Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser
Distributed control for reconfigurable FPGA systems: A high-level design approach. ReCoSoC (2012)
Hana Krichene, Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser
Broadcast with mask on a massively parallel processing on a chip. HPCS (2012)
Gilberto Ochoa-Ruiz, Ouassila Labbani-Narsis, El-Bay Bourennane, Sana Cherif, Samy Meftali, Jean-Luc Dekeyser
Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: A Xilinx EDK case study. ReConFig (2012)
Imran Rafiq Quadri, Abdoulaye Gamatié, Pierre Boulet, Samy Meftali, Jean-Luc Dekeyser
Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: Advantages, limitations and alternatives. J. Syst. Archit. 58 (5) (2012)
Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Jean-Luc Dekeyser, Eric Senn, Smaïl Niar
An efficient power estimation methodology for complex RISC processor-based platforms. ACM Great Lakes Symposium on VLSI (2012)
Venkatasubramanian Viswanathan, Benjamin Nakache, Rabie Ben Atitallah, Maurice Nakache, Jean-Luc Dekeyser
Dynamic reconfiguration of modular I/O IP cores for avionic applications. ReConFig (2012)
Pamela Wattebled, Jean-Philippe Diguet, Jean-Luc Dekeyser
Membrane-based design and management methodology for parallel dynamically reconfigurable embedded systems. ReCoSoC (2012)
Rabie Ben Atitallah, Éric Piel, Smaïl Niar, Philippe Marquet, Jean-Luc Dekeyser
A fast MPSoC virtual prototyping for intensive signal processing applications. Microprocess. Microsystems 36 (3) (2012)
Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Smaïl Niar, Eric Senn, Jean-Luc Dekeyser
Fast and accurate hybrid power estimation methodology for embedded systems. DASIP (2011)
Mouna Baklouti, Manel Ammar, Philippe Marquet, Mohamed Abid, Jean-Luc Dekeyser
A model-driven based framework for rapid parallel SoC FPGA prototyping. International Symposium on Rapid System Prototyping (2011)
Majdi Elhaji, Brahim Attia, Abdelkrim Zitouni, Rached Tourki, Samy Meftali, Jean-Luc Dekeyser
FeRoNoC: Flexible and extensible Router implementation for diagonal mesh topology. DASIP (2011)
Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Jean-Luc Dekeyser
A system level power consumption estimation for MPSoC. SoC (2011)
Chiraz Trabelsi, Rabie Ben Atitallah, Samy Meftali, Jean-Luc Dekeyser, Abderrazek Jemai
A Model-Driven Approach for Hybrid Power Estimation in Embedded Systems Design. EURASIP J. Embed. Syst. 2011 (2011)
Yassine Aydi, Mouna Baklouti, Mohamed Abid, Jean-Luc Dekeyser
A multi-level design methodology of multistage interconnection network for MPSOCs. Int. J. Comput. Appl. Technol. 42 (2/3) (2011)
Antonio Wendell De Oliveira Rodrigues, Frédéric Guyomarc'h, Jean-Luc Dekeyser, Yvonnick Le Menach
Automatic Multi-GPU Code Generation applied to Simulation of Electrical Machines CoRR (2011)
Vincent Aranega, Anne Etien, Jean-Luc Dekeyser
Using an Alternative Trace for QVT. Electron. Commun. Eur. Assoc. Softw. Sci. Technol. 42 (2011)
Antonio Wendell De Oliveira Rodrigues, Frédéric Guyomarc'h, Jean-Luc Dekeyser
Programming Massively Parallel Architectures using MARTE: a Case Study CoRR (2011)
Antonio Wendell De Oliveira Rodrigues, Frédéric Guyomarc'h, Jean-Luc Dekeyser
A Modeling Approach based on UML/MARTE for GPU Architecture CoRR (2011)
Sana Cherif, Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser
High level design of adaptive distributed controller for partial dynamic reconfiguration in FPGA. DASIP (2011)
Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Smaïl Niar, Eric Senn, Jean-Luc Dekeyser
Hybrid system level power consumption estimation for FPGA-based MPSoC. ICCD (2011)
George Afonso, Rabie Ben Atitallah, Alexander Loyer, Jean-Luc Dekeyser, Nicolas Bélanger, Martial Rubio
A prototyping environment for high performance reconfigurable computing. ReCoSoC (2011)
Abdoulaye Gamatié, Sébastien Le Beux, Éric Piel, Rabie Ben Atitallah, Anne Etien, Philippe Marquet, Jean-Luc Dekeyser
A Model-Driven Design Framework for Massively Parallel Embedded Systems. ACM Trans. Embed. Comput. Syst. 10 (4) (2011)
George Afonso, Rabie Ben Atitallah, Nicolas Bélanger, Martial Rubio, Stephan Stilkerich, Jean-Luc Dekeyser
Toward generic and adaptive avionic test systems. AHS (2011)
Adolf Samir Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser
Modélisation UML/MARTE de SoC et analyse temporelle basée sur l'approche synchrone. Vers l'exploration à haut niveau de l'architecture. Tech. Sci. Informatiques 30 (9) (2011)
Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser
Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis. DSD (2010)
Mouna Baklouti, Yassine Aydi, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA. J. Syst. Archit. 56 (7) (2010)
Imran Rafiq Quadri, Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Samy Meftali, Jean-Luc Dekeyser
Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation. Int. J. Embed. Syst. 4 (3/4) (2010)
Vincent Aranega, Jean-Marie Mottu, Anne Etien, Jean-Luc Dekeyser
Traceability for Mutation Analysis in Model Transformation. MoDELS (Workshops) (2010)
Adolf Samir Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser
Correct and energy-efficient design of SoCs: The H.264 encoder case study. SoC (2010)
Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser
IP Based Configurable SIMD Massively Parallel SoC. FPL (2010)
Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid
Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip. ARC (2010)
Majdi Elhaji, Abdelkrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, Rached Tourki
A Low power and highly parallel implementation of the H.264 8 × 8 transform and quantization. ISSPIT (2010)
Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser
Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation. DASIP (2010)
Antonio Wendell De Oliveira Rodrigues, Frédéric Guyomarc'h, Yvonnick Le Menach, Jean-Luc Dekeyser
Parallel Sparse Matrix Solver on the GPU Applied to Simulation of Electrical Machines CoRR (2010)
Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser
High level modeling of Dynamic Reconfigurable FPGAs. Int. J. Reconfigurable Comput. 2009 (2009)
Vincent Aranega, Jean-Marie Mottu, Anne Etien, Jean-Luc Dekeyser
Traceability Mechanism for Error Localization in Model Transformation. ICSOFT (1) (2009)
Adolf Samir Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser
Model-Driven Design of Embedded Multimedia Applications on SoCs. DSD (2009)
Hajer Chtioui, Rabie Ben Atitallah, Smaïl Niar, Jean-Luc Dekeyser, Mohamed Abid
A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC. DSD (2009)
Abdoulaye Gamatié, Éric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser
Model-Driven Engineering and Formal Validation of High-Performance Embedded Systems. Scalable Comput. Pract. Exp. 10 (2) (2009)
Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser
Study and integration of a parametric neighbouring interconnection network in a massively parallel architecture on FPGA. AICCSA (2009)
Yassine Aydi, Ramzi Tligue, Maissa Elleuch, Mohamed Abid, Jean-Luc Dekeyser
A multi level functional verification of multistage interconnection network for MPSOC. ICECS (2009)
Vincent Aranega, Jean-Marie Mottu, Anne Etien, Jean-Luc Dekeyser
Using Trace to Situate Errors in Model Transformations. ICSOFT (Selected Papers) (2009)
Adolf Samir Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser
MARTE-based Design of a Multimedia Application and Formal Analysis. FDL (2008)
Imran Rafiq Quadri, Pierre Boulet, Samy Meftali, Jean-Luc Dekeyser
Using an MDE Approach for Modeling of Interconnection Networks. ISPAN (2008)
Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser
MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs. ESTIMedia (2008)
Abdoulaye Gamatié, Éric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser
Synchronous Modeling and Analysis of Data Intensive Applications. EURASIP J. Embed. Syst. 2008 (2008)
Abdoulaye Gamatié, Éric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser
Modeling and Formal Validation of High-Performance Embedded Systems. ISPDC (2008)
Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Jean-Luc Dekeyser
Safe design of high-performance embedded systems in an MDE framework. Innov. Syst. Softw. Eng. 4 (3) (2008)
Julien Taillard, Frédéric Guyomarc'h, Jean-Luc Dekeyser
A Graphical Framework for High Performance Computing Using An MDE Approach. PDP (2008)
Sebastien Revol, Safouan Taha, François Terrier, Alain Clouard, Sébastien Gérard, Ansgar Radermacher, Jean-Luc Dekeyser
Unifying HW Analysis and SoC Design Flows by Bridging Two Key Standards: UML and IP-XACT. DIPES (2008)
Jehangir Khan, Smaïl Niar, Atika Rivenq, Yassin Elhillali, Jean-Luc Dekeyser
An MPSoC architecture for the Multiple Target Tracking application in driver assistant system. ASAP (2008)
Safouan Taha, Ansgar Radermacher, Sébastien Gérard, Jean-Luc Dekeyser
MARTE: UML-based Hardware Design from Modelling to Simulation. FDL (2007)
Éric Piel, Philippe Marquet, Jean-Luc Dekeyser
Model Transformations for the Compilation of Multi-processor Systems-on-Chip. GTTSE (2007)
Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser
Multiple Abstraction Views of FPGA to Map Parallel Applications. ReCoSoC (2007)
Rabie Ben Atitallah, Éric Piel, Smaïl Niar, Philippe Marquet, Jean-Luc Dekeyser
Multilevel MPSOC simulation using an MDE approach. SoCC (2007)
Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser
A Design Flow to Map Parallel Applications onto FPGAs. FPL (2007)
Philippe Marquet, Simon Duquennoy, Sébastien Le Beux, Samy Meftali, Jean-Luc Dekeyser
Massively parallel processing on a chip. Conf. Computing Frontiers (2007)
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser
An MPSoC Performance Estimation Framework Using Transaction Level Modeling. RTCSA (2007)
Safouan Taha, Ansgar Radermacher, Sebastien Gerard, Jean-Luc Dekeyser
An Open Framework for Detailed Hardware Modeling. SIES (2007)
Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Jean-Luc Dekeyser
Model Transformations from a Data Parallel Formalism towards Synchronous Languages. FDL (2007)
Ouassila Labbani, Éric Rutten, Jean-Luc Dekeyser
Safe Design Methodology for an Intelligent Cruise Control System with GPS. VTC Fall (2006)
Éric Piel, Philippe Marquet, Julien Soula, Jean-Luc Dekeyser
Real-time systems for multiprocessor architectures. IPDPS (2006)
Sébastien Le Beux, Philippe Marquet, Ouassila Labbani, Jean-Luc Dekeyser
FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar. DSD (2006)
Ouassila Labbani, Éric Rutten, Jean-Luc Dekeyser, Pierre Boulet
UML2 Profile for Modeling Controlled Data Parallel Applications. FDL (2006)
Rabie Ben Atitallah, Smaïl Niar, Alain Greiner, Samy Meftali, Jean-Luc Dekeyser
Estimating Energy Consumption for an MPSoC Architectural Exploration. ARCS (2006)
Rabie Ben Atitallah, Lossan Bonde, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser
Multilevel MPSoC Performance Evaluation Using MDE Approach. SoC (2006)
Ahmad Chadi Aljundi, Jean-Luc Dekeyser, M. Tahar Kechadi, Isaac D. Scherson
A universal performance factor for multi-criteria evaluation of multistage interconnection networks. Future Gener. Comput. Syst. 22 (7) (2006)
Lossan Bonde, Pierre Boulet, Jean-Luc Dekeyser
Traceability and Interoperability in Models Transformations. FDL (2005)
Arnaud Cuccuru, Jean-Luc Dekeyser, Philippe Marquet, Pierre Boulet
Towards UML 2 Extensions for Compact Modeling of Regular Complex Topologies. MoDELS (2005)
Pierre Boulet, Arnaud Cuccuru, Jean-Luc Dekeyser, Ashish Meena
Model Driven Engineering for Regular MPSoC Co-design. ReCoSoC (2005)
J. Vennin, S. Penain, Luc Charest, Samy Meftali, Jean-Luc Dekeyser
Embed Scripting inside SystemC. FDL (2005)
Samy Meftali, Jean-Luc Dekeyser, Isaac D. Scherson
Scalable Multistage Network for Multiprocessor System-on-Chip Design. ISPAN (2005)
Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet
Mode-Automata Based Methodology for Scade. HSCC (2005)
Éric Piel, Philippe Marquet, Julien Soula, Jean-Luc Dekeyser
Asymmetric Scheduling and Load Balancing for Real-Time on Linux SMP. PPAM (2005)

Jean-Luc Dekeyser.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Jean-Luc Dekeyser